Method for fabricating dishing free shallow isolation trenches

Details Method for fabricating dishing free shallow isolation trenches Method for fabricating dishing free shallow isolation trenches

1997-12-17

1999-07-13

Dang, Trung

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438424, 438435, 438692, 148DIG50, H01L 2176

Patent

active

059239930

ABSTRACT:
A fabrication process for manufacturing integrated circuits with isolation trenches. The process includes the use of two nitride layers and an oxide layer formed by high density plasma oxidation, to provide isolation trenches free of dishing. The isolated regions are useable for fabrication microelectronic circuit devices, such as MOS transistors or flash memory devices.

REFERENCES:
patent: 5498565 (1996-03-01), Gocho et al.
patent: 5665202 (1997-09-01), Subramanian et al.
patent: 5721173 (1998-02-01), Yano et al.
patent: 5728621 (1998-03-01), Zheng et al.
Boyd, John M., "A One-Step Shallow Trench Global Planarization Process Using Chemical Mechanical Polishing," Journal of the Electrochemical Society, vol. 144 No. 5, p. 1838, May 1997.

Affiliated with

Also associated with

Rating

Method for fabricating dishing free shallow isolation trenches does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for fabricating dishing free shallow isolation trenches, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating dishing free shallow isolation trenches will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2287602