Method for fabricating diffusion self-aligned short channel MOS

Details Method for fabricating diffusion self-aligned short channel MOS Method for fabricating diffusion self-aligned short channel MOS

1976-02-20

1977-12-13

Rutledge, L. Dewayne

Metal treatment

Compositions

Heat treating

29571, 148187, 357 41, 357 42, 357 91, H01L 21265, H01L 2978

Patent

active

040626997

ABSTRACT:
A diffusion self-aligned, short channel device may be fabricated by ion implantation of an n-type channel region within a p-type substrate. A p-type dopant is then implanted in and driven through a portion of the n-type channel region to form an impurity region. A diffusion self-aligned n-type channel region is then disposed in the p-type impurity region and in the n-type channel region. The method allows for the simultaneous fabrication of a channel implanted MOSFET as well as a standard MOSFET. The resulting diffusion self-aligned, short channel device is a high gain, high speed small device which can be simply combined and fabricated with channel-implanted depletion devices and low body effect devices in an integrated circuit.

REFERENCES:
patent: 3756861 (1973-09-01), Payne et al.
patent: 3775191 (1973-11-01), McQuhae
patent: 3793088 (1974-02-01), Eckton, Jr.
patent: 3845495 (1974-10-01), Cauge et al.
patent: 3895390 (1975-07-01), Meiling et al.
patent: 3909320 (1975-09-01), Cauge et al.
patent: 3924265 (1975-12-01), Rodgers
patent: 3933529 (1976-01-01), Goser
patent: 3988761 (1976-10-01), Kanazawa
patent: 4007478 (1977-02-01), Yagi
Chou, "Self-Registered Si Electrode FET," IBM Tech. Discl. Bull., vol. 14, No. 1, June, 1971, p. 250.

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