Fishing – trapping – and vermin destroying
Patent
1994-12-29
1997-01-07
Tsai, Jey
Fishing, trapping, and vermin destroying
437 15, 437 60, 437904, H01L 2170, H01L 2700
Patent
active
055916619
ABSTRACT:
A novel process is taught for forming diodes in a process which simultaneously forms MOS or CMOS devices. These diodes have relatively low breakdown voltage, making them suitable for ESD protection devices or as voltage reference diodes. In alternative embodiments, novel low breakdown voltage devices are fabricated in a similar fashion as MOS devices but with doping levels such that the inherent bipolar device has a low breakdown voltage characteristic. In alternative embodiments, novel vertical bipolar transistors are taught, as are SCR devices, having low breakdown voltage characteristics. In one embodiment of this invention, a low breakdown voltage device is integrated directly with a standard MOS transistor, allowing the low breakdown voltage device to trigger the turn on of the standard MOS device, thereby providing large current capacity controlled by the low breakdown voltage device.
REFERENCES:
patent: 3667009 (1972-05-01), Rugg
patent: 3787717 (1974-01-01), Fischer et al.
patent: 4081292 (1978-03-01), Aoki et al.
patent: 4312680 (1982-01-01), Hsu
patent: 4357178 (1982-11-01), Bergeron et al.
patent: 4366522 (1982-12-01), Baker
patent: 4400711 (1983-08-01), Avery
patent: 4412237 (1983-10-01), Matsumura
patent: 4677735 (1987-07-01), Malhi
patent: 4712152 (1987-12-01), Iio
patent: 4763184 (1988-08-01), Krieger et al.
patent: 4786955 (1988-11-01), Plus et al.
patent: 4806999 (1989-02-01), Strauss
patent: 4875130 (1989-10-01), Huard
patent: 4916085 (1990-04-01), Frisina
patent: 4937645 (1990-06-01), Ootsuka et al.
patent: 5065212 (1991-11-01), Ohata et al.
patent: 5081514 (1992-01-01), Ueoka
patent: 5144518 (1992-09-01), Miyazaki
patent: 5182220 (1993-01-01), Ker et al.
patent: 5182621 (1993-01-01), Hinooka
patent: 5254866 (1993-10-01), Ogoh
patent: 5272097 (1993-12-01), Shiota
Internal Chip ESD Phenomena Beyond the Protection Circuit in IEEE/IRPS 1988 pp. 19-25.
New ESD Protection Concept for VLSI CMOS Circuits Avoiding Circuit Stress 1991 EOS ESD Symposium Proceedings, pp. 74-82.
Caserza Steven F.
Tsai Jey
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