Method for fabricating crown capacitors for a dram cell

Details Method for fabricating crown capacitors for a dram cell Method for fabricating crown capacitors for a dram cell

1995-12-27

1996-08-06

Tsai, H. Jey

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170, H01L 2700

Patent

active

055433456

ABSTRACT:
A method is provided for fabricating a single crown electrode for a capacitor for semiconductor memory devices. A conductive layer is formed over a multi-layer gate and insulation structure. The conductive layer includes a portion extending through a contact hole to thereby electrically connect the conductive layer with an active region of a transistor formed in the substrate Next, a novel groove is etched in the conductive layer between adjacent memory cells. Sidewall spacers are formed on the groove. The conductive layer is anisotropically etched using the spacers as an etching mask, thereby forming a plurality of electrodes having upright portions. The etching exposes the first insulation layer in the area under the grooves, but leaves a thickness of the base conductive layer to form the bottom of the electrode. The spacers then are removed and a conformal dielectric layer is formed over the surface. Lastly, a top plate electrode is formed over the conformal dielectric layer.

REFERENCES:
patent: 5192702 (1993-03-01), Tseng
patent: 5266512 (1993-11-01), Kirsch
patent: 5372965 (1994-12-01), Ryou
patent: 5380673 (1995-01-01), Yang et al.
patent: 5389560 (1995-02-01), Park
patent: 5389568 (1995-02-01), Yun
patent: 5399518 (1995-03-01), Sim et al.
patent: 5443993 (1995-08-01), Park et al.

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