Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – On insulating substrate or layer
Patent
1995-04-03
1997-06-24
Niebling, John
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
On insulating substrate or layer
148DIG150, 257511, 257525, 257555, 257569, 257574, 438322, H01L 21265
Patent
active
056416911
ABSTRACT:
A method is described for fabricating a complementary, vertical bipolar semiconducting structure. An N+ silicon island and a P+ silicon island separated by a first oxide layer are formed on a sapphire substrate. An NPN junction device is formed on the N+ silicon island by epitaxially growing an N-type silicon layer on the N+ silicon island. Then, a P region is created in the N-type silicon layer. An N+ region created in the P region completes the NPN junction device. Similarly, a PNP junction device is formed by epitaxially growing a P-type silicon layer on the P+ silicon island. Then, an N region is created in the P-type silicon layer. A P+ region created in the N region completes the PNP junction device.
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Cartagena Eric N.
Walker Howard W.
Fendelman Harvey
Kagan Michael A.
Lipovsky Peter A.
Niebling John
Pham Long
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