Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Thinning of semiconductor substrate
Reexamination Certificate
2001-03-15
2002-10-22
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Thinning of semiconductor substrate
C438S311000, C438S406000, C438S977000, C257S347000
Reexamination Certificate
active
06468880
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of a Silicon on insulator (SOI) devices and more particularly to a method for fabricating complementary silicon on insulator (CSOI) devices that can be partially depleted and fully depleted (or accumulated) using wafer bonding.
2) Description of the Prior Art
Typical prior art bulk silicon such as diodes, field effect transistors (FETs) and bipolar transistors formed on a silicon wafer are subject to parasitic effects resulting from other bulk devices in close proximity and from vertical structural asymmetry. These parasitic effects include voltage limitations and cross-device interference.
Consequently, typical bulk semiconductor processes, especially FET processes that include both p-type FETs (PFETs) and n-type FETS (NFETs) and commonly referred to as CMOS, require dedicated structures to localize and reduce parasitic effects. These specialized structures include providing surface diffusions referred to as guard rings, individual doped wells (N-wells and/or P-wells) and including a buried insulator.
Silicon on insulator (SOI) devices have been dubbed as the next successor to the reigning Complementary Metal On Silicon (CMOS) devices. Silicon on insulator (SOI) has excellent isolation properties. Silicon on insulator (SOI) has existed for almost two decades, but still improved methods for making silicon on insulator (SOI) devices are needed to advance the technology.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 6,084,271(Yu et al.) shows a silicon on insulator (SOI) process using wafer bonding and STI's. U.S. Pat. No. 4,169,000(Riseman) shows a STI air gap and a wafer bonded thereover. U.S. Pat. No. 6,071,803(Rutten et al.) shows a contact to a buried SOI process using wafer bonding and STI's. U.S. Pat. No. 6,013,936(Colt, Jr.) teaches a double SOI device. U.S. Pat. No. 5,484,738(Chu et al.) teaches a bonded SOI device/process.
Thus, there is a need for individually isolated semiconductor devices that may be integrated into a single circuit on a single chip.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method to form a silicon on insulator (SOI) device.
It is an object of the present invention to provide a method to form a silicon on insulator (SOI) device that uses wafer bonding technique.
It is an object of the present invention to provide a method to form a silicon on insulator (SOI) device that uses wafer bonding technique that can be use to form fully and partially depleted complementary devices on the same wafer.
It is an object of the present invention to provide a method to form silicon on insulator devices that use either controlled Si wafer back grinding process or a controlled Wet Si wafer etch.
Briefly, the invention describes a method for a silicon on insulator (SOI) structure by forming shallow trench isolation (STI) regions on a first wafer, wafer bonding the first and a second wafer together, backside grinding the second wafer, patterning the second wafer to form second trenches in the second wafer, and depositing an insulator in the second trenches to isolate the active areas (e.g., silicon) of the remaining second wafer.
The method preferably comprises the following steps. A first substrate is provided having an insulating layer over a first side of the first substrate. The first substrate has a second side. A second substrate is provided having first trenches in a first side. The second substrate has a second side. We form first isolation regions (e.g., STI) that fill the trenches in the second substrate. Next, we bond the first and second substrate together by bonding the insulating layer to the first isolation regions and the second substrate. Then, preferably the second substrate is thinned by a process that removes material from the backside of the second substrate. Then, a stop layer is formed over the second side of the second substrate. The stop layer and the second side of the second substrate are patterned to form second trenches in the second substrate. The second trenches have sidewalls at least partially defined by the isolation regions and the second trenches expose the second insulating layer. The second trenches define first active regions over the first isolation regions (STI) and define second active regions over the insulating layer. Next, the second trenches are filled with an insulator material to from second isolation regions. The filling of the second trenches with an insulator material preferably comprises forming an oxide layer over the stop layer and filling the second trenches. The oxide layer is preferably chemical-mechanical polished (CMP) using the stop layer as a CMP stop. Next, the stop layer is removed. Lastly, fully depleted devices are formed in and on the first active regions. Also, partially depleted devices are formed in and on the second active regions. The fully depleted devices and the partially depleted devices are comprised of MOS FET devices comprised of source and drain regions and gate electrodes.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 4169000 (1979-09-01), Riseman
patent: 5102819 (1992-04-01), Matsushita et al.
patent: 5484738 (1996-01-01), Chu et al.
patent: 6010950 (2000-01-01), Okumura et al.
patent: 6013936 (2000-01-01), Colt, Jr.
patent: 6071803 (2000-06-01), Rutten et al.
patent: 6084271 (2000-07-01), Yu et al.
patent: 6313507 (2001-11-01), Lee
patent: 6329239 (2001-12-01), Koh et al.
patent: 6335214 (2002-01-01), Fung
patent: 6399973 (2002-06-01), Roberds
patent: 6417030 (2002-07-01), Buynoski et al.
Cha Randall Cher Liang
Goh Wang Ling
Lee Tae Jong
Lim Yeow Kheng
See Alex
Chartered Semiconductor Manufacturing Ltd.
Fahmy Wael
Pike Rosemary L. S.
Saile George O.
Stoffel William J.
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