Method for fabricating complementary enhancement and depletion m

Fishing – trapping – and vermin destroying

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437 51, 437 56, 437 57, 437979, 148DIG82, 148DIG150, H01L 21265

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active

053004434

ABSTRACT:
A method for fabricating complementary enhancement and depletion mode field ffect transistors on a single substrate comprises the steps of: a) patterning a structure of a layer of silicon formed on an insulating substrate to form first, second, third, and fourth silicon islands; b) doping the second island with a p-type dopant; c) doping the third island with a p-type dopant; d) doping the fourth island with an n-type dopant; e) forming a first electrically insulating gate layer on the third and fourth islands; f) forming a second electrically insulating gate on the first and second islands; g) forming an electrically conductive gate over the first and second electrically insulating gate layers; h) doping the second island with an n-type dopant; i) doping the fourth island with an n-type dopant; j) doping the first and third islands with a p-type dopant; and k) doping the first and third islands with a p-type dopant to transform the first island into a p-type enhancement mode field effect transistor, the second island into a n-type enhancement mode field effect transistor, the third island into a p-type depletion mode field effect transistor, and the fourth island into an n-type depletion mode field effect transistor.

REFERENCES:
patent: 4002501 (1977-01-01), Tamura
patent: 4385937 (1983-05-01), Ohmura
patent: 4395726 (1983-07-01), Maeguchi
patent: 4682055 (1987-07-01), Upadhyayula
patent: 4816893 (1989-03-01), Mayer et al.
patent: 5024965 (1991-06-01), Chang et al.
patent: 5245207 (1993-07-01), Mikoshiba et al.

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