Method for fabricating CMOS semiconductor devices

Details Method for fabricating CMOS semiconductor devices Method for fabricating CMOS semiconductor devices

1992-09-16

1995-01-17

Thomas, Tom

Fishing, trapping, and vermin destroying

437 56, 437 57, H01L 21265

Patent

active

053825322

ABSTRACT:
A method for fabricating semiconductor devices wherein polysilicon gates for complementary-type field-effect semiconductor devices are formed of polysilicon to which impurity doped simultaneously to the polysilicon deposition; the both gates having the dual N.sup.+ /P.sup.+ polysilicon gate structure, so that the both N- and P-channel transistors are formed as the surface-channel type ones; and therefore, the off-characteristic, the short channel effect, and the controllability of threshold voltage are progressed. More specifically, N- and P-channel MISFETs are provided on a common semiconductor substrate (1); N-type polysilicon (9) doped with N-type impurity is adopted as the gate electrode for the N-channel MISFET; P-type polysilicon (8) doped with P-type impurity is adopted as the gate electrode for the P-channel MISFET; and a narrow region preventing the mutual diffusion of impurities is provided between portions of respective polysilicon.

REFERENCES:
patent: 5026657 (1991-06-01), Lee et al.
C. K. Lau et al., "A High Performance CMOS Process with Half-Micron Gate and Novel Low-Parasitic Salicide Interconnect Scheme," Hewlett-Packard Laboratories, 1985, pp. 12-13.
J. Y. -C. Sun et al., "0.5 um-Channel CMOS Technology Optimized for Liquid-Nitrogen-Temperature Operation," IEEE, 1986, pp. 236-239.
N. Kasai et al., "0.25 um CMOS Technology Using P+ Polysilicon Gate PMOSFET," IEEE, 1987, pp. 367-370.
B. Davari et al., "A High Performance 0.25 um CMOS Technology," IEEE, 1988, pp. 56-59.

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