Method for fabricating CMOS in P substrate with single guard rin

Details Method for fabricating CMOS in P substrate with single guard rin Method for fabricating CMOS in P substrate with single guard rin

1981-07-29

1983-05-31

Roy, Upendra

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

29571, 29576B, 29578, 148 15, 357 42, 357 91, H01L 21225, B01J 1700

Patent

active

043859470

ABSTRACT:
CMOS transistors are fabricated in a P substrate by applying a first mask with an opening for introducing N type impurities to form a well, applying a second mask layer of oxidation inhibiting material over the region in which the transistors are to be formed; applying a third mask layer over the well, introducing P type impurities into the surface of the substrate using the second and third masking layers to form a guard ring except in the N- well regions and the regions in which the N channel MOS transistors are to be formed, oxidizing the substrate using said second mask to form a thick oxide layer on said substrate except on the transistor regions with the guard ring vertically displaced from the regions in which the transistors are to be formed, introducing P impurities in the channel region of the CMOS transistors and forming CMOS transistors in said transistor regions.
A CMOS process capable of the fabrication of N and P channel devices with channel lengths down to the submicron region by the proper adjustment of doping levels and implant doses in the N type well and the P and N channel regions, with no major changes in the basic process flow.

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