Method for fabricating chip modules

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including adhesive bonding step

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

438119, H01L 2144

Patent

active

057892784

ABSTRACT:
A method for forming a chip module such as a multi chip module or a memory module is provided. The multi chip module includes a substrate configured to mount a plurality of semiconductor dice thereon. The substrate includes raised contact members formed in patterns that correspond to the locations of bond pads on the dice. An anisotropic conductive adhesive layer is formed between the contact members on the substrate and the bond pads on the dice to secure the dice to the substrate and form an electrical connection therebetween. In addition, an underfill layer can be formed between the dice and substrate to fill the gap therebetween and further secure the dice to the substrate. Conductors and input/output pads formed on the substrate form electrical paths to and from the contact members. To form a memory module, one or more multi chip modules can be mounted to a supporting substrate having an edge connector in electrical communication with the conductors and with contact members on the substrates.

REFERENCES:
patent: 4899921 (1990-02-01), Bendat et al.
patent: 4937653 (1990-06-01), Blonder et al.
patent: 4992850 (1991-02-01), Corbett et al.
patent: 5072289 (1991-12-01), Sugimoto et al.
patent: 5206585 (1993-04-01), Chang et al.
patent: 5249450 (1993-10-01), Wood et al.
patent: 5262718 (1993-11-01), Svendsen et al.
patent: 5326428 (1994-07-01), Farnworth et al.
patent: 5408190 (1995-04-01), Wood et al.
patent: 5419807 (1995-05-01), Akram et al.
patent: 5428223 (1995-06-01), Higashi et al.
patent: 5440240 (1995-08-01), Wood et al.
patent: 5458694 (1995-10-01), Nuyen
patent: 5474620 (1995-12-01), Nath et al.
patent: 5478779 (1995-12-01), Akram
patent: 5483174 (1996-01-01), Hembree et al.
patent: 5483741 (1996-01-01), Akram et al.
patent: 5487999 (1996-01-01), Farnworth
patent: 5519332 (1996-05-01), Wood et al.
patent: 5578526 (1996-11-01), Akram et al.
patent: 5578537 (1996-11-01), Chang et al.
patent: 5607818 (1997-03-01), Akram et al.
patent: 5634267 (1997-06-01), Farnworth et al.
patent: 5661042 (1997-08-01), Fang et al.
patent: 5668059 (1997-09-01), Christie et al.
patent: 5678301 (1997-10-01), Gochnour et al.
Yamamoto, Yasuhikio et al., "Evaluation of New Micro-Connection System Using Microbumps", Nitto Denko Corp., Technical Paper, ISHM '93 Proceedings, pp. 370-378.
Miyake, Kiyoshi et al., "Connectivity Analysis of New `Known Good Die` Connection System Using Microbumps", Technical Report, Nitto Denko Corp., pp. 1-7, 1994.
Zilber, G. et al., "Slimcase--A Thin Chip Size, Integrated Circuit Package", ShellCass Ltd., MANHAT, Brochure, pp. 2-8, 1996.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for fabricating chip modules does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for fabricating chip modules, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating chip modules will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1176457

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.