Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2002-12-30
2004-03-02
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S754000
Reexamination Certificate
active
06699769
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for fabricating a capacitor of a semiconductor device; and, more particularly, to a method for fabricating a capacitor using an electrochemical deposition method and Ce(NH
4
)
2
(NO
3
)
6
solution.
DESCRIPTION OF RELATED ART
At present, semiconductor memory devices are largely divided into a random access memory (RAM) and a read-only memory (ROM). Particularly, RAM is divided again into a dynamic RAM (DRAM) and a static RAM. Among them, DRAM which is composed of unit cells, each including a transistor and a capacitor, is most favorable for high degree of integration and, accordingly, DRAM is leading the semiconductor memory market.
Meanwhile, due to the great progress in the degree of integration, the capacity of a memory has increased four times as high as it used to be three years ago. Nowadays, 256 mega or 1 giga-class DRAM is about to be mass-produced.
As the integration of DRAM becomes higher, the memory cell area should be smaller. In case of 256M DRAM, the memory cell area should be less than 0.5 &mgr;m
2
, and its capacitor area, which is a basic constituent of the cell, should become less than 0.3 &mgr;m
2
. For this reason, the technology used in the conventional processing for a semiconductor over 256M DRAM is now facing a technological limitation.
That is, when a capacitor used in a 64M DRAM is fabricated using such a dielectric material as SiO
2
/Si
3
N
4
, in order to secure the required capacitance, the area occupied by the capacitor becomes more than six times as big as the cell area, even though it is assumed that the thin films of the capacitor are formed thinnest.
Accordingly, researchers are studying to seek a method for increasing the surface area of a capacitor to secure the required capacitance. To increase the surface area of a bottom electrode of the capacitor, various technologies using a three-dimensional stacked capacitor, trench-type capacitor or hemispherical polysilicon layer are suggested.
However, when a capacitor is fabricated using such a conventional dielectric material as oxide nitride oxide (ONO) in a semiconductor memory device over 256M DRAM, the capacitance cannot be increased more than that, because the thin film cannot be any thinner. Also, since the structure of the capacitor cannot be made more complex than now, the surface area of the capacitor cannot be increased any further, either. This is because the complex structure makes the process too complicated, as well as causing a problem of high production cost and dropping throughput.
To solve the above problems, dielectric materials having a higher dielectric constant than the conventional ONO dielectric material are adopted as a dielectric substance for the capacitor. The newly adopted high dielectric materials includes Ta
2
O
5
, (Ba,Sr)TiO
3
(BST), Al
2
O
3
, SrTiO
3
, and TaON.
However, the dielectric constant of the above high dielectric materials changes according to what material is used for a bottom electrode of the capacitor. As far as found out, the dielectric characteristic becomes best when the high dielectric material is put on metal.
Accordingly, such metal as Pt, Ir, Rh and Ru are used for an electrode of the capacitor, instead of polysilicon which has been used for a bottom electrode conventionally.
When a metallic material is used for an electrode of a capacitor, the biggest problem in the capacitor fabrication process is the etching of the metallic material, which is for the bottom electrode of the capacitor.
Referring to
FIGS. 1A
to
1
E, a conventional method for forming a Ru bottom electrode using a metal organic chemical vapor deposition (MOCVD) method. First, with reference to
FIG. 1A
, a first inter-layer insulation layer
11
is formed on a semiconductor substrate
10
, which is completed with a predetermined process, such as formation of transistor and bit lines. Then, a contact hole is formed to expose a predetermined surface of the semiconductor substrate
10
by etching the first inter-layer insulation layer
11
.
With reference to
FIG. 1B
, a polysilicon
12
is formed on the first inter-layer insulation layer
11
including the contact hole. Then, the polysilicon is recessed in a predetermined depth by performing etch-back to form a polysilicon plug
12
buried in a predetermined part of the contact hole.
Subsequently, titanium (Ti) is deposited on the entire surface of the substrate including the contact hole, and rapid thermal process (RTP) is performed to make the silicon atoms of the polysilicon plug
12
react with the titanium to form a titanium silicide (Ti-silicide)
13
on the polysilicon plug
12
. The remaining non-reacted titanium is removed. Here, the titanium silicide
13
forms an ohmic contact with the polysilicon plug
12
and the subsequent bottom electrode.
Subsequently, a titanium nitride (TiN)
14
is formed on the entire structure including the contact hole. Then, the titanium nitride
14
remains only in the contact hole by performing chemical-mechanical polishing (CMP) or etch-back, until the surface of the first inter-layer insulation layer
11
is exposed. Here, the titanium nitride
14
performs the role of a barrier layer for preventing the diffusion of materials between the bottom electrode and the polysilicon plug
12
or the semiconductor substrate
10
, or for preventing the diffusion of oxygen in the subsequent annealing process.
Referring to
FIG. 1C
, an oxide layer
15
is deposited on the entire structure, which is obtained by completing the above processes and includes the first inter-layer insulation layer
11
and the titanium nitride
14
, to form a bottom electrode. Then, a trench
16
is formed by going through masking and etching processes.
Referring to
FIG. 1D
, a ruthenium (Ru) bottom electrode
17
is deposited by performing MOCVD on the entire surface including the trench
16
. Then, with reference to
FIG. 1E
, the Ru bottom electrode
17
is removed except the Ru bottom electrode deposited on the inside of the trench to thereby isolate the bottom electrode.
Referring to
FIG. 1F
, a high dielectric thin film
18
and a top electrode
19
are formed sequentially on the entire structure including the Ru bottom electrode
17
. This way, the capacitor fabrication process is completed.
The Ru bottom electrode which is deposited in the MOCVD method has a shortcoming that the fine thin film is not obtained, because the deposition process is performed at a low temperature. However, when RTP is performed in the hope of making the thin film fine, the Ru thin film becomes cracked.
If the Ru bottom electrode is cracked, the titanium nitride under the Ru bottom electrode is exposed. The exposed nitride forms a thin film having a low dielectric constant, and during the annealing, oxidation is performed, thus dropping the performance of the capacitor. This problem is inevitable as long as the Ru thin film is deposited at a low temperature to enhance the step coverage of the Ru thin film.
Moreover, when the Ru thin film is deposited at a low temperature, high step coverage is required to form a dielectric thin film and a top electrode successively in the trench as well as the Ru bottom electrode.
Therefore, the Ru bottom electrode has a limitation in its thickness, and when the bottom electrode is too thin, the characteristic as an electrode is dropped. Particularly, this becomes a big problem, as the degree of the integration becomes higher. Thus, a new method for forming a bottom electrode to overcome the limitation is required.
The methods for forming a bottom electrode are represented by a method that forms a platinum (Pt) electrode using electrochemical deposition. However, this method has a shortcoming that the leakage current of the Pt bottom electrode is not stable to the high dielectric materials, just except (Ba,Sr)TiO
3
(BST). So, it is not widely applied.
In conclusion, among the methods for forming a bottom electrode using the various high dielectric materials, the method for forming Ru bottom electrode using electrochemical depositi
Choi Hyung-Bok
Song Chang-Rock
Fourson George
Hynix / Semiconductor Inc.
Jacobson & Holman PLLC
Pham Thanh V
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