Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Patent
1999-02-25
2000-10-24
Hardy, David
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
257751, 257752, 257763, H01L 2348
Patent
active
061371793
ABSTRACT:
An electrical interconnection structure is described for semiconductor integrated circuits on substrates, and is applicable to making bit lines for COB DRAM circuits. After forming semiconductor devices (field effect transistors), in and on device areas on a substrate, a planar insulating layer is formed. Contact openings are etched in the planar insulating layer to the devices areas. A conformal Ti/TiN barrier layer is deposited on the surface of the planar insulating layer and in the contact openings. A refractory metal tungsten (W) layer is deposited and selectively etched back to the barrier layer to form metal plugs in the contact openings. The Ti/TiN barrier layer is then patterned to form electrical interconnections. This electrical interconnection structure is particularly useful for making, concurrently, the local interconnections for integrated circuits and the bit lines for a capacitor-over-bit line (COB) DRAM device. The reduced height of the Ti/TiN barrier layer significantly reduce the aspect ratio for multilevel contacts, allowing for fabricating of integrated circuits, such DRAM circuits, with higher density and improved reliability. The Ti/TiN and W interconnect structure also allows subsequent higher temperature processing as is necessary for making the capacitors for the COB DRAM.
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Ackerman Stephen B.
Hardy David
Ortiz Edgardo
Saile George O.
Taiwan Semiconductor Manufacturing Company
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