Method for fabricating capacitor in semiconductor device

Details Method for fabricating capacitor in semiconductor device Method for fabricating capacitor in semiconductor device

2002-12-12

2004-03-16

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making passive device

Planar capacitor

C438S240000, C438S250000

Reexamination Certificate

active

06706607

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for fabricating an integrated circuit in a semiconductor device; and, more particularly, to a method for fabricating a capacitor in a semiconductor device.
DESCRIPTION OF RELATED ARTS
As a degree of integration of a memory device, particularly, a dynamic random access memory (DRAM), increases progressively, a memory cell area that is a basic unit for storing information significantly decreases.
The decrease in the memory cell area brings another reduction of an area for cell capacitance, thereby decreasing a sensing margin and a sensing speed. Moreover, there results in another problem of decreased durability for soft error that occurs due to &agr;-particles. Therefore, it is necessary to develop a method for obtaining sufficient capacitance within a limited cell area.
The capacitance of a capacitor is defined by the following mathematic equation.
C=∈·As/d
  Eq. 1
Herein, ∈, As and d denote a dielectric constant, an effective surface area of an electrode and a distance between the electrodes, respectively.
Hence, there has been developed several approaches to increase the capacitance of-the capacitor by increasing the surface area of the electrode, decreasing a thickness of a dielectric thin layer and increasing the dielectric constant.
Among these approaches, it is firstly considered an approach of increasing the surface area of the electrode. Capacitors in various forms of a three-dimensional structure such as a concave, a cylinder, a multi-layered fin and so on are aimed to increase the effective surface area of the electrode within the limited area. However, as a degree of integration of a semiconductor device becomes extensively high, this approach confronts another limitation in that the effective surface area of the electrode cannot be increased sufficiently.
Also, another approach of decreasing the thickness of the dielectric material to minimize the distance (d) between the electrodes is limited as well since leakage currents increase as the thickness of the dielectric thin layer gets decreased.
Therefore, it is a recent trend in increasing mainly the dielectric constant of the dielectric thin layer, and thus, obtaining the sufficient capacitance of the capacitor. A traditionally fabricated capacitor uses a silicon oxide layer or a silicon nitride layer as a source for the dielectric thin layer. However, it is more increasingly used in today a capacitor with a metal-insulator-poly si (hereinafter referred as to MIS) structure wherein it uses a high-k dielectric material, e.g., Ta
2
O
5
as a dielectric thin layer.
FIGS. 1
is a cross-sectional view illustrating a typical method for fabricating a capacitor having a cylinder structure in a semiconductor device.
Referring to
FIG. 1
, an inter-layer insulation layer
12
is formed on a substrate
10
previously constructed with an activation area
11
, and then, a contact hole that passes through the inter-layer insulation layer
12
and is contacted to the activation area
11
of the substrate
10
is formed. Subsequently, the contact hole is filled with a conductive material, forming a contact plug
13
. On top of the contact plug
13
, a capacitor insulation layer is formed as with the size for forming a capacitor.
Next, the capacitor insulation layer is selectively etched to expose the contact plug
13
and form a capacitor hole.
A polysilicon lower electrode
14
is formed inside the capacitor hole, and the capacitor insulation layer is then removed. After forming the polysilicon lower electrode
14
, a nitride layer
15
is formed by nitridating a surface of the polysilicon lower electrode
14
through the use of Si
3
N
4
plasma gas or a rapid thermal process.
A Ta
2
O
5
layer is formed on the nitride layer
15
as a dielectric thin layer
16
, and an upper electrode
17
is overlaid subsequently.
Herein, the surface of polysilicon lower electrode
14
is nitridated with use of the Si
3
N
4
plasma gas before forming the Ta
2
O
5
layer for forming the dielectric thin layer
16
. This prior nitridation is to prevent oxygen from penetrating into the polysilicon lower electrode
14
and oxidizing it while carrying out a thermal process in an atmosphere of oxygen in order to improve a dielectric constant.
As a high degree of integration is progressively embodied in a semiconductor device, and particularly, as a capacitor has a three-dimensional structure in a concave form or a cylinder form, it is difficult to nitride the surface of the polysilicon lower electrode
14
with a constant thickness. That is, a typical plasma process or a rapid thermal process does not allow the nitride layer to be formed stably on the polysilicon lower electrode
14
.
If the nitride layer is not formed properly, oxygen gets penetrated into the bottom structure of the capacitor, e.g., polysilicon lower electrode, and oxidizes the bottom structure. This problem eventually reduces a confidence level in the capacitor fabrication.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for fabricating a capacitor, wherein a nitride layer is stably formed on a lower electrode and sufficient capacitance and improved leakage current characteristics are obtained.
In accordance with an aspect of the present invention, there is provided A method for fabricating a capacitor in a semiconductor device, including the steps of: forming a lower electrode on a substrate; forming a nitride-based first dielectric thin layer on the lower electrode; forming a second dielectric thin layer by depositing an A
1
2
O
3
layer on the nitride-based first dielectric thin layer; forming a third dielectric thin layer on the second dielectric thin layer; and forming an upper electrode on the third dielectric thin layer.


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