Method for fabricating bipolar transistors

Details Method for fabricating bipolar transistors Method for fabricating bipolar transistors

1999-07-08

2002-09-03

Lee, Eddie (Department: 2815)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Using epitaxial lateral overgrowth

C438S321000, C438S343000, C438S345000

Reexamination Certificate

active

06444536

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to bipolar transistors, and, in particular, to an improved method for fabricating bipolar transistors such as double polysilicon bipolar transistors.
BACKGROUND OF THE INVENTION
Double polysilicon bipolar transistors are important components on many applications. Such devices are used, for example, in high speed, low power amplifiers for wireless communication systems and in other high end applications.
A bipolar transistor (sometimes referred to as a “double poly” transistor) is formed with two layers of polysilicon: a first polysilicon layer for base electrodes and a second polysilicon layer for the emitter electrode. The advantage of using polysilicon, rather than single crystal silicon, is self-alignment of the emitter, improved forward current gain, reduced collector-base parasitic capacitance and reduced spacing between the emitter and base electrodes. Double polysilicon bipolar transistors and methods for making them are described in detail in applicant's U.S. Pat. No. 5,428,243 issued Jun. 27, 1995 and entitled “Bipolar Transistor With A Self-Aligned Heavily Doped Collector Region and Base Link Regions” and U.S. Pat. No. 5,320,972 issued Jun. 14, 1994 and entitled “Method of Forming a Bipolar Transistor”, which are incorporated herein by reference. Related structures and methods are described in H. K. Park et al., “High Speed Polysilicon Emitter-Base Bipolar Transistor”, IEEE Electron Device Letters, EDL-7, No. 12 (December 1986).
An often used method for making double polysilicon bipolar transistors is that described in the U.S. Pat. No. 5,428,243 patent. In essence, a semiconductor workpiece is formed comprising a stack of N-doped polysilicon layers topped by patterned field oxide isolation regions. The stack includes a heavily doped buried layer overlaid by a lightly doped epitaxial layer including a device well region.
A relatively thick sacrificial layer of silicon dioxide (~1500 angstroms) is deposited on the workpiece and patterned for opening a minimum dimension space wherein the emitter stripe is to be formed.
Subsequent to patterning the emitter stripe, an etch is performed to remove both the oxide and a portion of the underlying doped polysilicon. This etch, which is carried out without an etch stop, extends into the collector layer. The etch can produce a significant and undesirable trench in the underlying collector.
After the etch, a “link implant” is implanted into the open stripe, and a sidewall spacer of dielectric material is formed against the walls of the opening that will ultimately isolate the emittter from the base contacts.
An intrinsic base is then implanted into the reduced size open stripe, and the emitter material is deposited into the open stripe. A transistor can now be formed by activating the implants and metallizing the active regions.
While this now conventional process has worked well for many applications, it does present problems and can be improved. One problem is the trenching of the exposed emitter strip during removal of the base polysilicon. Another problem is that the link implant, which electrically connects the intrinsic base region of the transistor to the base contact region, cannot be more heavily doped than the intrinsic region. This introduces additional base contact resistance. Thirdly, the conventional process is not well adapted for integration into a process which also includes fabrication of CMOS transistors (a “BICMOS” process). Accordingly, there is a need for an improved process for fabricating double polysilicon bipolar transistors.
SUMMARY OF THE INVENTION
In accordance with the invention, a bipolar transistor is fabricated by disposing a sacrificial layer over the conventional semiconductor workpiece. The sacrificial layer is patterned into a stripe corresponding to the emitter stripe, and the base contacts are formed in relation to the sacrificial stripe. The stripe is removed, and the base and emitter are formed. In the preferred embodiment, the sacrificial layer is a stack of layers providing etch selectivity.


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