Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of...
Reexamination Certificate
2004-02-20
2004-11-09
Tsai, H. Jey (Department: 2812)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
C438S338000, C438S373000
Reexamination Certificate
active
06815301
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for fabricating a bipolar transistor, and more particularly relates to a method for fabricating a bipolar transistor in which epitaxial growth is not used.
In recent years, as the cellular phone market and the mobile equipment market have been expanding, reduction in costs for bipolar transistors as a high-speed operation device has been required. Hereinafter, a known method for fabricating a bipolar transistor will be described with reference to the accompanying drawings.
First, a method for fabricating a bipolar transistor according to a first known example will be described with reference to
FIGS. 7A through 7E
(see, e.g., Japanese Examined Patent Publication No. 59-50227).
FIGS. 7A through 7E
are cross-sectional views illustrating respective steps of a method for fabricating a bipolar transistor according to the first known example.
First, as shown in
FIG. 7A
, a p-type semiconductor single crystalline substrate
500
made of silicon and doped with boron at a concentration of 1×10
15
atoms/cm
3
is prepared.
Next, as shown in
FIG. 7B
, using a mask (not shown) having an opening portion corresponding to a buried-collector-layer-forming region, arsenic ions are implanted into the semiconductor single crystalline substrate
500
at an injection dose of 5×10
15
atoms/cm
2
. An injection angle in this ion implantation process is slightly tilted (by about 7 degree) from the normal direction of the semiconductor single crystalline substrate
500
. By the ion implantation process, a buried collector layer
501
is formed in a predetermined region of the semiconductor single crystalline substrate
500
. Thereafter, an epitaxial layer
502
which is doped with phosphorus at a concentration of about 1×1016 atoms/cm
3
and has a thickness of about 1 &mgr;m is formed over the semiconductor single crystalline substrate
500
. Note that after the epitaxial layer
502
has been formed, arsenic ions introduced into the buried collector layer
501
are diffused in a lower potion of the epitaxial layer
502
, so that the buried collector layer
501
expands.
Next, as shown in
FIG. 7C
, using a mask (not shown) having an opening portion through which a collector-wall-forming region of the epitaxial layer
502
is exposed, phosphorus ions are implanted into the semiconductor single crystalline substrate
500
at an injection dose of 2×10
15
atoms/cm
2
, thereby forming a collector wall layer
503
in a predetermined region of the epitaxial layer
502
. Thereafter, thermal treatment at a temperature of 1000° C. is performed to the semiconductor single crystalline substrate
500
for 30 minutes, thereby expanding the collector wall layer
503
so that the collector wall layer
503
has a thickness enough to reach the buried collector layer
501
.
Next, as shown in
FIG. 7D
, using a mask (not shown) having an opening portion through which a base-layer-forming region of the epitaxial layer
502
is exposed, boron ions are implanted into a surface portion of the epitaxial layer
502
at an injection dose of 3×10
13
atoms/cm
2
, thereby forming a base layer
504
in a predetermined region of the surface portion of the epitaxial layer
502
. Then, using a mask (not shown) having an opening portion through which an emitter-layer-forming region of the base layer
504
is exposed, arsenic ions are implanted into the semiconductor single crystalline substrate
500
at an injection dose of 4×10
15
atoms/cm
2
, thereby forming an emitter layer
505
in a predetermined region of a surface portion of the base layer
504
. Thereafter, thermal treatment at a temperature of 850° C. is performed to the semiconductor single crystalline substrate
500
for about 30 minutes, thereby activating impurities introduced into the base layer
504
and the emitter layer
505
, respectively.
Next, as shown in
FIG. 7E
, an oxide film
506
made of a BPSG (borophosphosilicate glass) film having a thickness of about 1 &mgr;m is deposited over the semiconductor single crystalline substrate
500
using CVD (chemical vapor deposition) to protect a surface of a bipolar transistor including the epitaxial layer
502
, the base layer
504
, the emitter layer
505
and the like. Thereafter, a collector electrode
507
, a base electrode
508
and an emitter electrode
509
(i.e., electrodes of a bipolar transistor) connected to the collector wall layer
503
, the base layer
504
and the emitter layer
505
, respectively, and made of aluminum are formed by sputtering. Thus, a bipolar transistor is completed. Note that although not shown in
FIGS. 7A through 7E
, the elemental bipolar transistor described above is surrounded using an appropriate isolation technique, for example, by a dielectric isolation region or a PN junction isolation region, so as to be electrically isolated from other semiconductor elements to be formed in the periphery of the elemental bipolar transistor.
Next, a method for fabricating a bipolar transistor according to a second known example will be described with reference to
FIGS. 8A through 8E
(see, e.g., Japanese Unexamined Patent Publication No. 2001-291781).
FIGS. 8A through 8E
are cross-sectional views illustrating respective steps of a method for fabricating a bipolar transistor according to the second known example. Note that in
FIGS. 8A through 8E
, the same members as those described in the first known example are identified by the same reference numerals.
As shown in
FIG. 8A
, a p-type semiconductor single crystalline substrate
500
made of silicon and doped with boron at a concentration of 1×10
15
atoms/cm
3
is prepared.
Next, as shown in
FIG. 8B
, using a mask (not shown) having an opening portion corresponding to a collector-layer-forming region, phosphorus ions are implanted into the semiconductor single crystalline substrate
500
at a dose of 5×10
12
atoms/cm
2
. An injection angle in this ion implantation process is slightly tilted (by about 7 degree) from the normal direction of the semiconductor single crystalline substrate
500
. By this ion implantation process, a collector layer
510
is formed in a predetermined region of the semiconductor single crystalline substrate
500
.
Next, as shown in
FIG. 8C
, thermal treatment at a temperature of 1100° C. is performed to the semiconductor single crystalline substrate
500
for 100 minutes, thereby activating the collector layer
510
while expanding the collector layer
510
to a predetermined depth.
Thereafter, process steps shown in
FIGS. 8D and 8E
are performed. The process steps are the same as those of
FIGS. 7C through 7E
used for the first known example.
In the method for fabricating a bipolar transistor according to the first known example, the epitaxial layer
502
is formed. Therefore, fabrication costs are increased. Moreover, because of the existence of the epitaxial layer
502
which is unique to the bipolar transistor, properties of an MOS transistor vary if one or more fabrication process steps for fabricating a bipolar transistor are added to existing CMOS (complementary metal oxide semiconductor) processes.
Moreover, in the second known example, a collector layer
510
is formed using an n-type well, instead of an epitaxial layer. In this case, to ensure the breakdown voltage of a bipolar transistor, the collector layer
510
has to be formed at a great depth in the downward direction from a surface of the semiconductor single crystalline substrate
500
. Therefore, drive-in diffusion at a high temperature is normally performed. However, an impurity introduced through ion implantation is diffused not only in the downward direction but also in the lateral direction. Therefore, taking it into consideration that the collector layer
510
(see
FIG. 8B
) formed on the surface portion of the semiconductor single crystalline substrate
500
through ion implantation expands also in the lateral direction (see
FIG. 8C
) due to a high temperature drive-in diffusion, a clearance between adjacent
Matsushita Electric - Industrial Co., Ltd.
McDermott Will & Emery LLP
Tsai H. Jey
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