Method for fabricating bipolar-MOS devices

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437 31, 437 34, 437 41, 437 46, 437 57, 437 89, 437 99, H01L 21225, H01L 2176

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active

048792551

ABSTRACT:
The present invention is a method for fabricating bipolar-MOS devices having n-MOSs, p-MOSs and bipolar transistors, each fabricated in a respective silicon single crystal layer grown in openings formed in a field oxide layer covering a silicon substrate. Over the field oxide layer, having openings where the active devices should be fabricated, is applied an epitaxial growth of silicon. By this operation, single crystal layers are formed in the openings, and a polysilicon layer is formed on the field oxide layer. The polysilicon layer is patterned to form the source and drain contact electrodes of the FETs and the base and collector contact electrodes of the bipolar transistors simultaneously. To the active areas, contact electrodes for the p-MOS, and base contact electrodes of the npn bipolar transistors are simultaneously implanted with p type impurities by ion implantation. The active areas, contact electrodes for the n-MOS, and the collector contact electrodes of the npn bipolar transistors are simultaneously implanted with n type impurities by ion implantation. For the pnp transistors, an inverse process of the above is applied. By such a method, the process for fabricating the bipolar-MOS device is simplified, and the operation of the device is improved.

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patent: 4752589 (1988-06-01), Schaber

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