Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Including isolation structure
Reexamination Certificate
2002-12-13
2004-11-09
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Including isolation structure
C438S326000
Reexamination Certificate
active
06815305
ABSTRACT:
This application claims the benefit of the Korean Application No. P2002-57804 filed on Sep. 24, 2002, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device in which isolation layers and a bipolar junction transistor collector are simultaneously formed by an epitaxial growth process during a process of fabricating a BiCOMS.
2. Discussion of the Related Art
Generally, circuits of a semiconductor device are formed based on a complementary metal oxide semiconductor CMOS transistor. Because of a limited capability of the CMOS transistor to drive a current, however, a BiCOMS circuit is being used for a semiconductor device of superhigh speed, in which a bipolar junction transistor BJT is used along with the CMOS transistor to be applied to some circuits in need of high current driving capability.
At this instance, to apply both of the BJT and the CMOS transistor to one semiconductor chip, additional processes such as an epitaxial growth process and photo mask and photo etching processes should be performed during a CMOS transistor fabricating process. These additional processes can increase a production cost while reducing the yield rate.
A process of fabricating a related art BiCOMS will be described with reference to accompanying drawings.
FIGS. 1A and 1D
are plane views illustrating a process of fabricating a related art BiCMOS.
When the BiCMOS process is performed in which a BJT and a CMOS logic circuit are formed on the same substrate, a deep trench isolation DTI process and a shallow trench isolation STI process should also be performed. The DTI process is for reducing latch-up immunity of a BJT and a substrate parasitic capacitance and the STI process is for insulating the CMOS.
A process of forming an isolation film during the related art BiCMOS fabricating process is as follows.
First, as shown in
FIG. 1A
, on a semiconductor substrate
1
, first and second insulating layers
2
and
3
are formed in order so as to prevent the growth of silicon. At this time, the first insulating layer
2
is an oxidation film and the second insulating layer
3
is a nitride hard mask.
Then, the second insulating layer
3
is selectively etched by a photolithography process, thereby defining a DTI region, the region for reducing latch-up immunity of the BJT and a substrate parasitic capacitance.
Subsequently, a predetermined portion of the first insulating layer
2
is etched with predetermined depth using the second insulating layer
3
, being selectively patterned, as a mask. In this way, a trench for forming the DTI region is formed.
Subsequently, as shown in
FIG. 1B
, the DTI region
4
is formed by filling up the trench with an insulating material and etching it back. At this instance, the nitride hard mask, i.e., the second insulating layer
3
a
, becomes thinner during the etch-back process.
Then, as shown in
FIG. 1C
, as a photo-mask process for an STI process, a photoresist (not shown) is applied to the entire surface of the substrate and a photoresist pattern is formed to define the STI region. And, the first and second insulating layers
2
and
3
being exposed are selectively etched. At this time, a nitride hard mask, i.e., the second insulating layer
3
b
, maintains the same thickness without being thinner during the etching process.
A trench
5
for forming the STI region is formed by selectively etching the exposed semiconductor substrate
1
using the first and second insulating layers
2
and
3
, being patterned, as a mask.
Then, as shown in
FIG. 1D
, the STI region
6
is formed by filling up the trench
5
with an insulating material and etching it back. At this time, a nitride hard mask, i.e., the second insulating layer
3
c
, maintains the same thickness without being thinned during the etching process.
As described above, generally, in the process of forming a device isolating film during the related art BiCMOS fabricating process, the trench of the etched semiconductor substrate is filled with the insulating film and then is evened.
A process of fabricating a BiCMOS according to the related art, however, has the following problems or disadvantages.
First, in the process of fabricating the BiCMOS of the related art, an additional photo mask process for forming a STI region should be performed after a DTI region is formed. Also, after the STI region being formed, another process for reducing a resistance of a collector should be performed to improve the high frequency characteristic of BJT. Finally, a process of implanting an ion of high energy and high degree of density should also be separately performed from a process of forming a well of the CMOS. Hence, the overall process steps increase.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method for fabricating a semiconductor device that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for fabricating a semiconductor device in which isolation films and a collector of a BJT are simultaneously formed by an epitaxtial growth process during a process of fabricating a BiCMOS.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a method for fabricating a semiconductor device of the present invention includes processes of forming a first mask layer on a semiconductor substrate, etching a predetermined portion of the semiconductor substrate with predetermined depth using the first mask layer, forming a first isolation layer on a side face of the etched semiconductor substrate, forming a first epitaxial layer doped with a plurality of layers by epitaxial growth of the exposed portion of the semiconductor substrate, forming a second mask layer on the first epitaxial layer, and forming a second epitaxial layer by epitaxial growth of a portion of the first epitaxial layer.
The first mask layer has a laminated structure of an oxidation film and a nitration film for the use of a hard mask. A portion of the semiconductor substrate, the portion being etched by the first mask layer, includes first and second isolation layers having different depth from each other.
The first epitaxial layer is a collector of the BJT and the second epitaxial layer is a well region of a CMOS.
The first epitaxial layer having a height lower than the first isolation layer is formed by simultaneously performing two processes: a process of implanting ion impurities in the first epitaxial layer, and a process of epitaxial growth. The first epitaxial layer has either a two-layered structure of a doped epitaxial layer and an undoped epitaxial layer or a three-layered structure of an undoped epitaxial layer, a doped epitaxial layer, and an undoped epitaxial layer.
The second mask layer is formed of an oxidation layer for a hard mask and acts as a second isolation layer being formed inside the second epitaxial layer. Also, the second mask layer has the same thickness as that of the second epitaxial layer.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
D.L. Harame, et al. “Si/SiGe Epitaxial-Base Transistors-Part II: Process Integration and Analog Applications.
Elms Richard
Hynix / Semiconductor Inc.
Piper Rudnick LLP
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