Method for fabricating BiCMOS device

Details Method for fabricating BiCMOS device Method for fabricating BiCMOS device

1996-06-21

1997-12-02

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 79, 437162, H01L 218249

Patent

active

056935552

ABSTRACT:
A method for fabricating a bipolar complementary metal oxide semiconductor device, includes a first step of forming a three-layered substrate of p.sup.-
.sup.+
.sup.- type or n.sup.- /p.sup.+ /p.sup.- type and forming p- and n-wells to be adjacent to each other to the bottom of the top layer of the three-layered substrate; a second step of isolating the p- and n-wells from each other and defining a region for a bipolar transistor on one side to separate base/emitter regions from each other; a third step of defining a gate region to form a metal- oxide semiconductor transistor in each of the p- and n-wells and forming collector/emitter regions in the bipolar transistor region; and a fourth step of forming an n-type metal oxide semiconductor transistor, a p-type metal oxide semiconductor transistor and a bipolar transistor on the p-well, n-well and collector/emitter regions, respectively, and forming source/drain and base electrodes through diffusion by using a doped polycrystalline silicon sidewall spacer.

REFERENCES:
patent: 5015594 (1991-05-01), Chu et al.
patent: 5348896 (1994-09-01), Jang et al.
patent: 5407841 (1995-04-01), Liao et al.
patent: 5439833 (1995-08-01), Hebert et al.
"Process Integration Technology for sub-30ps ECL BiCMOS using Heavily Boron Doped Epitaxial Contact (HYDEC)" published in 1994 IEEE.
"A Half-micron Super Self-aligned BiCMOS Technology for High Speed Applications" published in 1992 IEEE.
"Double LDD Concave (LDC) Structure for Sub-half Micron MOSFET" published in 1988 IEEE.

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