Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1998-11-09
2001-11-27
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S431000, C438S439000, C438S445000, C438S448000
Reexamination Certificate
active
06323105
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method for fabricating an isolation structure including a shallow trench isolation (STI) structure with a local oxidation (LOCOS) isolation structure.
2. Description of Related Art
A device isolation structure is generally used to prevent carriers, such as electrons or electron-holes from drifting between two adjacent devices. Conventionally, isolation structures are formed between field effect transistors FETs, which usually are densely formed, so as to prevent a charge leakage of the FETs from occurring. These densely formed FETs can be, for example, a dynamic random access memory (DRAM) device. The isolation structures usually include several field oxide (FOX) structures distributed on a substrate surface. The FOX layers typically are formed by a local oxidation (LOCOS) method on the substrate surface.
FIG. 1
is a cross-sectional view of a conventional LOCOS structure with isolated FETs on a portion of a semiconductor substrate. In
FIG. 1
, on a substrate
100
, a FET
104
and a FET
106
are isolated by a FOX structure
102
. Each of the FETs
104
,
106
typically includes a gate on the substrate, a source region on one side of the gate in the substrate
100
, and a drain region on the other side of the gate in the substrate
100
. The FETs
104
,
106
belong to a part of a memory device, which also includes a capacitor and interconnects (not shown).
The FOX structure
102
can be formed by a LOCOS process before the FETs
104
,
106
are formed. The FOX structure
102
is typically formed by sequentially forming an oxide layer (not shown) and a silicon nitride layer (not shown) over the substrate
100
. The silicon nitride layer is patterned to expose a portion of the oxide layer, on which the FOX structure
102
is desired to form later. A LOCOS process is performed to oxide the exposed oxide layer so as to form the FOX structure
102
on the substrate
100
. Since the silicon nitride layer does not absorb oxidant, such water vapor, the portion covered by the silicon nitride layer is not oxidized so as to provide an active area for forming the FETs
104
,
106
. After removing the oxide layer, the FOX structure
102
is formed on the substrate
100
. This process is called LOCOS process. However, oxidant can enter the rim region of the silicon nitride layer to form a bird's beak structure
108
, which is well known structure in the LOCOS process.
The bird's beak structure
108
consumes an available area for forming a memory cell, and the bird's beak structure
108
by itself has a poor isolation performance due to its small thickness. The FOX structure
102
formed by LOCOS process is not a good isolation structure for device with high integration, such as a memory device.
Another type of isolation structure called a shallow trench isolation (STI) structure is proposed to solve the problems of the FOX structure
102
.
FIGS. 2A-2F
are cross-sectional views, schematically illustrating a conventional fabrication processes for fabricating a STI structure. In
FIG. 2A
, a pad oxide layer
202
is formed on a semiconductor substrate
200
to protect the substrate surface. A silicon nitride layer
204
is formed by chemical vapor deposition (CVD) on the pad oxide layer
202
. A photoresist layer
208
with a pattern is formed on the silicon nitride
204
. In
FIG. 2B
, using the photoresist layer
208
as an etching mask, the silicon nitride layer
204
, the pad oxide layer
202
, and the substrate
200
are etched to form a trench
210
in the substrate
210
.
In
FIG. 2C
, after removing the photoresist layer
208
, a silicon oxide layer
212
is formed over the substrate
200
so as to fill the trench
210
. In
FIG. 2D
, using the silicon nitride layer
204
as a polishing stop point, a chemical mechanical polishing (CMP) process is performed to polish the silicon oxide layer
212
so that the silicon nitride layer
204
is exposed. A silicon oxide layer
212
a
remaining in the trench
210
of
FIG. 2B
forms a trench oxide plug. During the CMP process, since the silicon oxide layer
212
a
is softer than the silicon nitride layer
204
, the silicon oxide layer
212
a
has a dishing effect
214
due to its polishing rate is faster. In
FIG. 2E
, the silicon nitride layer
204
is removed but the silicon oxide layer
212
a
remains. In
FIG. 2F
, the pad oxide layer
202
is etched away by a hydrofluoric (HF) acid solution. A top portion of the silicon oxide layer
212
a
is also etched. In this current structure, an over etching usually occurs at the upper corners of the silicon oxide layer
212
a
abutting the substrate
200
to form a shoulder
216
. The shoulder
216
may cause a poor quality of a gate oxide layer formed subsequently and results in a decrease of the threshold voltage, which may further induce a kink effect due to an abnormal sub-threshold current.
Moreover, since the silicon oxide layer
212
a
is polished in the CMP process, a microscratch usually occurs on the top surface of the silicon oxide layer
212
a
. The dishing effect, the kink effect, and the microscratch may cause a problem of the device performance. Therefore, the STI structure still has its drawbacks for serving as an isolation structure.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method for forming an isolation structure with a solution to reduce the bird's beak structure of a LOCOS FOX structure.
It is another an objective of the present invention to provide a method for forming an isolation structure with a solution to reduce the dishing effect, the kink effect, and the microscratch in a STI structure.
In accordance with the foregoing and other objectives of the present invention, an improved method for fabricating an isolation structure by using both a STI process and a LOCOS process is provided. The improved method includes forming a first liner oxide layer over a substrate, on which a patterned hard material layer is formed. A hard spacer is formed on each sidewall of the hard material layer. A first thermal process is performed to form a LOCOS structure on the substrate other than the hard spacer and the hard material layer. Then, the hard spacer is removed so that a portion of the pad oxide on the substrate is exposed. A trench is formed in the substrate between the hard material layer and the LOCOS structure. A conformal second liner oxide layer is formed on the inner surface of the trench. The trench is preferably filled with a polysilicon layer, having a surface about as high as the substrate surface or higher. A second thermal process is performed to oxidize the polysilicon layer so as to merge the LOCOS structure to cover the surface of the polysilicon layer. The hard material layer is removed to form the isolation structure of the invention.
In accordance with the foregoing and other objectives of the present invention, an improved isolation structure including a STI structure and a LOCOS structure is provided. A LOCOS structure is located on a substrate surface. A trench is located on each side of the LOCOS structure. A liner oxide layer is located on the inner surface of the trench. A polysilicon plug fills in the trench. An isolation layer together with the LOCOS structure covers the polysilicon plug. Thus, the improved isolation structure includes the STI structure and the LOCOS structure.
REFERENCES:
patent: 5360753 (1994-11-01), Park et al.
patent: 5395790 (1995-03-01), Lur
patent: 5498566 (1996-03-01), Lee
patent: 5811315 (1998-09-01), Yindeepol et al.
patent: 5911109 (1999-06-01), Razouk et al.
patent: 6027984 (2000-02-01), Thakur et al.
patent: 6087241 (2000-07-01), St. Amand et al.
Chen Coming
Lin Tony
Jones Josetta I.
Niebling John F.
United Microelectronics Corp.
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