Method for fabricating an integrated circuit with multi-layer wi

Details Method for fabricating an integrated circuit with multi-layer wi Method for fabricating an integrated circuit with multi-layer wi

1984-05-11

1985-08-27

Ozaki, George T.

Metal working

Method of mechanical manufacture

Assembling or joining

29589, 29590, 29591, H01L 2128

Patent

active

045369496

ABSTRACT:
A programmable integrated circuit has multi-layer wiring with openings over fuses, and a fabrication method forms the openings for each fuse, to avoid damage due to the blowing off of the fuses. The forming of the openings is performed by etching each insulating layer on the fuses after it is formed over the pre-formed wiring-layers. This results in shorter etching time as compared to the prior art etching method where the openings are etched in all the layers for the whole depth in one process step. Because of the shorter time necessary for each etching, overetching and side-etching are reduced, thus providing the openings with more accurately determined dimensions, which provides higher yield for manufacturing the device. The contact holes and the windows for the bonding pads in each insulating layer are etched in the same fabrication step for forming the openings for the fuses in the same insulating layer. This requires no additional fabrication processes for the IC and results in no increase of the fabrication time and cost.

REFERENCES:
patent: 3564354 (1971-02-01), Aoki et al.
patent: 4198744 (1980-04-01), Nicolay
patent: 4387503 (1983-06-01), Aswell et a l.
patent: 4420504 (1983-12-01), Cooper et al.
patent: 4455194 (1984-06-01), Yabu et al.
patent: 4460914 (1984-07-01), te Velde et al.
patent: 4481263 (1984-11-01), Cooper et al.
patent: 4494135 (1985-01-01), Moussie

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