Method for fabricating an integrated circuit on a...

Details Method for fabricating an integrated circuit on a... Method for fabricating an integrated circuit on a...

2007-11-20

2007-11-20

Dang, Trung (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Recrystallized semiconductor material

C257SE21133, C257SE29139, C438S486000

Reexamination Certificate

active

11319793

ABSTRACT:
Integrated circuit device comprising a conductive layer and a poly-crystalline silicon layer, wherein the integrated circuit device further comprises an intermediate counter-stress layer. This intermediate counter-stress layer is arranged between the poly-crystalline silicon layer and the conductive layer, and enables stress-reduced crystallization of the poly-crystalline silicon layer. Further, the intermediate counter-stress layer is amorphous at and below a poly-silicon crystallization temperature.

REFERENCES:
patent: 6114200 (2000-09-01), Yew et al.
patent: 6146927 (2000-11-01), Yamanaka
patent: 6861320 (2005-03-01), Usenko
patent: 2003/0184705 (2003-10-01), Murade et al.
patent: 2004/0029343 (2004-02-01), Seidl et al.

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