Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
2000-02-04
2001-06-05
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S406000, C438S455000, C438S456000
Reexamination Certificate
active
06242319
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a method for fabricating an integrated circuit configuration.
Endeavors are generally made to produce an integrated circuit configuration with an ever higher packing density.
A reference by Y. Hayashi et al., titled “Fabrication of Three-Dimensional IC Using Cumulatively Bonded IC (CUBIC) Technology”, IEEE Symposium on VLSI Technology (1990), 95, describes a method for fabricating a three-dimensional integrated circuit configuration in which substrates containing semiconductor components are stacked one above the other. First, the semiconductor components are produced in the substrates. Each substrate is provided with a metalization plane that connects the semiconductor components of the substrate to one another. Tungsten pins are applied on each metalization plane. A first of the substrates is applied to a support substrate in such a way that its front side, on which the tungsten pins are disposed, adjoins the support substrate. A rear side of the first substrate is then thinned by grinding and provided with a further metalization plane. Depressions are produced in the rear side of the first substrate and their surfaces are provided with an Au—In alloy. A polymide layer is subsequently applied on the rear side of the first substrate. A second of the substrates is subsequently connected to the first substrate in such a way that the tungsten pins of the second substrate descend into the depressions on the rear side of the first substrate. The second substrate is aligned with respect to the first substrate with the aid of an infrared microscope. In order to connect the first substrate to the second substrate, the temperature is initially increased until the Au—In alloy melts. The temperature is then reduced to room temperature. The two substrates are pressed one on top of the other in the process. The support material is subsequently removed. The tungsten pins serve as contacts between the semiconductor components of the first substrate and the semiconductor components of the second substrate. The three-dimensional integration of substrates allows the integrated circuit configuration to have a particularly high packing density.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating an integrated circuit configuration that overcomes the above-mentioned disadvantages of the prior art methods of this general, which can be a three-dimensional circuit configuration and can have a high packing density.
The problem is solved by a method for fabricating an integrated circuit configuration, in which at least one first structure of the circuit configuration is produced in the region of a surface of a first substrate. At least one alignment structure, which scatters electron beams differently than its surroundings, is produced in the region of the surface of the first substrate. A second substrate, which is more transmissive to electron beams than the alignment structure, is connected to the first substrate in such a way that the second substrate is disposed above the surface of the first substrate. In order to align at least one mask with respect to the first structure, the position of the alignment structure is determined with the aid of electron beams. With the aid of the mask, at least one second structure of the circuit configuration is produced in the region of an upper surface of the second substrate, the upper surface being remote from the first substrate.
The second structure is thus produced in such a way that it assumes a predetermined position with respect to the first structure.
In contrast to an integrated circuit configuration which is produced in a single substrate, the integrated circuit configuration according to the invention can have a particularly high packing density since the second structure and the first structure may be semiconductor components and, at the same time, may be disposed one above the other, with the result that the integrated circuit configuration is a three-dimensional circuit configuration. A projection of the first structure onto the surface of the first substrate and a projection of the second structure onto the surface of the first substrate can overlap. The projection of the second structure can even lie completely in the projection of the first structure.
In contrast to Hayashi et al. (see above), the second substrate does not have to be aligned with respect to the first substrate, since the second structure is produced only after the connection of the two substrates. The alignment of substrates is subject to greater alignment inaccuracies than the alignment of masks for producing structures. Consequently, the integrated circuit configuration can be produced with a higher packing density than the integrated circuit configuration according to Hayashi et al.
If a plurality of chips each containing a first structure analogous to the first structure and a second structure analogous to the second structure are produced from the two substrates, masks can be produced for each individual chip, with the result that the second structures can be aligned independently of one another with respect to the associated first structures in each case. In contrast to this, in the case of the method according to Hayashi et al. (see above), all the second structures have to be aligned jointly with respect to the first structures, with the result that it is not possible to compensate for differing distances between the second structures or between the first structures, and the alignment inaccuracies between a respective one of the first structures and the associated second structure are greater. For a compromise between the speed of the fabrication method and the reduction of alignment inaccuracies, it lies within the scope of the invention to produce a respective mask for groups of chips.
In contrast to Hayashi et al., a support substrate is not necessary. Consequently, the risky removal of the support substrate from a side of a substrate that encompasses semiconductor components is avoided.
The alignment of the mask with the aid of electron beams is very accurate in comparison with the alignment of the second substrate with the aid of infrared radiation as described in Hayashi et al. On account of insignificant alignment inaccuracies of the mask, the position of the second structure with respect to the first structure can be set very accurately. Consequently, the circuit configuration can be fabricated with a high packing density.
The search for the position of the alignment structure can be limited to a small part of the first substrate, since, as is customary in semiconductor fabrication, it is possible to carry out a prealignment with the aid of the shape of the first substrate. Consequently, in order to determine the position of the alignment structure, only a small region of the second substrate is irradiated by electron beams, with the result that most of the second substrate, in which the second structure is produced, is not jeopardized by possible damage due to the electron beams.
The alignment structure may be composed e.g. of metal or metal silicide. The first substrate and the second substrate may contain e.g. a semiconductor material such as silicon or germanium.
With the aid of a further mask, which is aligned e.g. like the mask, a contact hole, which is filled with conductive material in order to form a contact, can be produced in the second substrate. The second structure is electrically connected to the first structure via the contact.
On account of insignificant alignment inaccuracies of the further mask, the contact can have a subsequently smaller cross section than the tungsten pins described in Hayashi et al., with the result that the integrated circuit configuration can be fabricated with a higher packing density.
The contact hole uncovers the first structure, and the conductive material of the contact can be deposited directly on the first structure, with the result that the contact can have a good connection to the fi
Hofmann Franz
Willer Josef
Greenberg Laurence A.
Lerner Herbert L.
Malsawma Lex H.
Siemens Aktiengesellschaft
Smith Matthew
LandOfFree
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