Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
2005-06-28
2005-06-28
Chang, Richard (Department: 3729)
Metal working
Method of mechanical manufacture
Electrical device making
C029S846000, C427S097100, C427S099300, C083S929100, C257S622000
Reexamination Certificate
active
06910268
ABSTRACT:
Vertical holes are created in streets separating individual integrated circuit (IC) dies formed on a semiconductor wafer, the holes spanning saw-lines along which the wafer is to be later cut to separate the IC die from one another to form individual IC chips. The holes are then filled with conductive material. After the wafer is cut along the saw-lines, portions of the conductive material on opposing sides of the saw-lines remain on peripheral edges of the IC chip to form signal paths between the upper and lower surfaces of the IC chips.
REFERENCES:
patent: 3648131 (1972-03-01), Stuby
patent: 3781683 (1973-12-01), Freed
patent: 3849872 (1974-11-01), Hubacher
patent: 4984358 (1991-01-01), Nelson
patent: 5185502 (1993-02-01), Shepherd et al.
patent: 5317479 (1994-05-01), Pai et al.
patent: 5371654 (1994-12-01), Beaman et al.
patent: 5373627 (1994-12-01), Grebe
patent: 5386341 (1995-01-01), Olson et al.
patent: 5442282 (1995-08-01), Rostoker et al.
patent: 5822856 (1998-10-01), Bhatt et al.
patent: 5832600 (1998-11-01), Hashimoto
patent: 5847445 (1998-12-01), Wark et al.
patent: 5914218 (1999-06-01), Smith et al.
patent: 5915170 (1999-06-01), Raab et al.
patent: 5969952 (1999-10-01), Hayashi et al.
patent: 5998864 (1999-12-01), Khandros et al.
patent: 6002163 (1999-12-01), Wojnarowski
patent: 6017613 (2000-01-01), Baum et al.
patent: 6051866 (2000-04-01), Shaw et al.
patent: 6059982 (2000-05-01), Palagonia et al.
patent: 6072190 (2000-06-01), Watanabe et al.
patent: 6080596 (2000-06-01), Vindasius et al.
patent: 6114221 (2000-09-01), Tonti et al.
patent: 6214641 (2001-04-01), Akram
patent: 6228676 (2001-05-01), Glenn et al.
patent: 6330164 (2001-12-01), Khandros et al.
patent: 6336269 (2002-01-01), Eldridge et al.
patent: 7-021968 (1995-01-01), None
patent: 7-333232 (1995-12-01), None
patent: WO 00/75985 (2000-12-01), None
Gregus, Jeffrey A., Maureen Y. Lau, Yinon Degani and King L. Tai, “Chip-Scale Modules for High-Level Integration in the 21st Century,”Bell Labs Technical Journal, Jul.-Sep. 1998, pp. 116-124.
Mehra, Amit, Zin Zhang, Arturo A, Ayón, Ian A. Waitz, Martin A. Schmidt, “Through-wafer Electrical Interconnect for Multilevel Microelectromechanical System Devices,”J. Vac. Sci. Technol. B 18(5), Sep./Oct. 2000, pp. 2583-2589.
“Through-Wafer Electrical Interconnects Compatible With Standard Semiconductor Processing,” mhtml:file://C:\TEMP\Eugene Chow hilton head.mht, Sep. 25, 2000.
Murphy, Tom, “Tru-Si Technologies Makes Wafer Stacking a Possibility,”Electronic News(1991), Dec. 6, 1999.
“2D Microcantilever Arrays with Through-Wafer Interconnects,” http://www.stanford.edu/ ˜emc/2dpicts.html, Dec. 14, 2000.
“Employment of the Deep Plasma Silicon Etching for the Production of New Microfluidic Components,” http://222.tu-dresden.de/etihm/english/research/hlt/ihm_eng/fo_pro_e/fra_e012.html, Dec. 15, 2000.
“Advanced Silicon Etched (ASE)”, http://www. stsystems.com/ase.html, Jan. 15, 2001.
Chang Richard
Fliesler & Meyer LLP
FormFactor Inc.
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