Semiconductor device manufacturing: process – Making passive device – Trench capacitor
Reexamination Certificate
2003-07-31
2004-11-23
Dang, T. (Department: 2823)
Semiconductor device manufacturing: process
Making passive device
Trench capacitor
C438S387000, C438S396000, C257S308000, C257S309000
Reexamination Certificate
active
06821861
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method for fabricating an electrode arrangement for charge storage having an outer trench electrode, which is formed along the wall of a trench provided in a substrate and is electrically insulated in the trench on both sides by a first and second dielectric; an inner trench electrode, which insulated in the trench by the second dielectric, serves as a counterelectrode to the outer trench electrode; and a substrate electrode, which, insulated by the first dielectric outside the trench, serves as a counter electrode to the outer trench electrode and which in the upper trench region is connected to the inner trench electrode.
BACKGROUND ART
An electrode arrangement of this type is known from Patent Abstracts of Japan vol. 010, No. 221 (E-424), Aug. 2, 1986 (1986-08-02) & JP 61 056445 A (Toshiba Corp), Mar. 22, 1986 (1986-03-22).
U.S. Pat. No. 5,985,729 has disclosed an electrode arrangement for charge storage, with electrode plugs, which are connected to substrate electrodes in the lower trench region, being provided in trenches. Folded counterelectrodes are provided in the trenches, insulated by a dielectric.
In the case of dynamic random access memories, 1-transistor cells which substantially comprise a storage capacitor and a select transistor, which connects a storage electrode to a bit line of the circuit arrangement in the dynamic random access memory, are used.
An increase in the integration density is associated with a reduction in the size of the components used in, for example, dynamic random access memories, and therefore it is necessary to reduce the size of the 1-transistor cells as well. Reducing the size of the cells leads to a geometric reduction in the size of the capacitors, resulting in a reduction in the charge stored.
Conventional storage capacitors are formed, inter alia, as trench capacitors, i.e. a trench is etched into a substrate layer and a dielectric and a storage electrode, for example doped polysilicon, are introduced. The counterelectrode used is, for example, a doped silicon substrate (buried plate).
FIG. 3
shows a trench capacitor in accordance with the prior art. In this case, a trench-like substrate electrode
301
is connected to a substrate connection device
107
. A filling electrode
302
is connected to the drain terminal of a select transistor
105
. A source terminal of the select transistor
105
is connected to an electrode connection device
106
. The select transistor
105
is driven via a gate terminal of the select transistor
105
, and can connect the filling electrode
302
to a bit line (not shown).
In the example shown in
FIG. 3
, the filling electrode
302
has a positive polarity, so that positive charge units
204
are located on the filling electrode
302
. Accordingly, negative charge units
203
are formed on the substrate electrode
301
. The total storable charge is therefore dependent on the thickness of a dielectric
104
, an electrode surface area and a material constant of the dielectric.
To increase a storage capacity, it is customary to reduce the thickness of the dielectric. The thickness of the dielectric cannot be reduced arbitrarily to avoid leakage currents. A variation in the magnitude of the storage capacitance can be achieved in particular by varying the surface area of the electrode arrangement of the storage capacitor.
It is therefore a drawback of conventional electrode arrangements that, in the event of a reduction in the feature size of random access memories, a capacitor surface area and, as a result, a capacitance of storage capacitors decreases.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a method for fabricating an electrode arrangement for charge storage which is designed in such a manner that an active surface area of the storage capacitor is increased in size.
This object is achieved by the method as claimed in claim
1
.
The electrode arrangement according to the invention therefore has the advantage that the active surface area of a storage capacitor in dynamic random access memories is increased.
A further advantage of the electrode arrangement according to the invention and of the method for forming the electrode arrangement consists in the fact that it is possible to achieve smaller feature sizes without a capacitance of storage capacitors decreasing in dynamic random access memories.
Furthermore, it is advantageous that, in the electrode arrangement according to the invention and with the method according to the invention for forming an electrode arrangement for charge storage, it is not necessary to reduce a thickness of a dielectric.
An increase in the leakage current density is advantageously avoided.
The essence of the invention is an electrode arrangement for charge storage which is based on a folded storage electrode, in which the charge which can be stored is significantly increased.
The subclaims give advantageous developments of and improvements to the corresponding subject matter of the invention.
Exemplary embodiments of the invention are illustrated in the drawings and are explained in more detail in the description which follows.
REFERENCES:
patent: 5047815 (1991-09-01), Yasuhira et al.
patent: 5106774 (1992-04-01), Hieda et al.
patent: 5432113 (1995-07-01), Tani
patent: 5753549 (1998-05-01), Lee
patent: 5985729 (1999-11-01), Wu
patent: 6022786 (2000-02-01), Franosch et al.
patent: 6417063 (2002-07-01), Petter et al.
patent: 61036965 (1986-02-01), None
patent: 61056445 (1989-03-01), None
Goldbach Matthias
Hecht Thomas
Dang T.
Infineon - Technologies AG
Jenkins & Wilson & Taylor, P.A.
LandOfFree
Method for fabricating an electrode arrangement for charge... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating an electrode arrangement for charge..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating an electrode arrangement for charge... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3338386