Semiconductor device manufacturing: process – Making device array and selectively interconnecting
Reexamination Certificate
2002-08-12
2003-10-28
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
C438S131000, C438S600000, C438S467000
Reexamination Certificate
active
06638794
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to a method of a fabricating a semiconductor device, and more particularly to a method of fabricating an anti-fuse in programmable interconnections.
BACKGROUND
With the rapid development of integrated circuit technologies, there has been a trend to reduce the scale of a device. Thus, semiconductor technologies have increased the integrated circuit density on a chip. The semiconductor devices manufactured in and on the semiconductor substrate are very closely spaced. The alignment, lithography technologies are more important than ever due to the density of the packing density is continuously increased. During the formation of the ICs, programmable devices are typically formed on a certain area for replacing the element having defects. For example, the programmable device is employed to replace the defected DRAM. The programmable device is typically consisted of a selecting transistor and an anti-fuse. The selecting transistor may select the anti-fuse that wish to be used and then the input voltage conducts the anti-fuse. One of the prior arts may refer to U.S. Pat. No. 6,040,608, entitled “Field Effect Transistor for One-Time Programmable Nonvolatite Memory Element.”
Up to now, there are various ways to form the anti-fuse. One of the methods is to conduct the anti-fuse by biasing high voltage. Another method is to alter the conductivity of the anti-fuse by using laser. One of the articles may refer to IEEE, 38
th
Annual International Reliability Physics Symposium, 2000, page 169, “One Time Programmable Drift Anti-fuse Cell Reliability.” Wherein the art disclosed that laser anti-fuse is one of the solutions for SRAM and DRAM redundancy. The un-programmed structure used to form the anti-fuse has an intrinsically high resistance, by applying a programmable current, the electrical resistance through the anti-fuse material is greatly reduced providing a conductive link between metallizations. Typical the anti-fuse materials include amorphous silicon, amorphous carbon, carbon, germanium and so on.
One of the arts related to an anti-fuse process that compatible with the CMOS process. Another further prior art includes NMOS connected to an anti-fuse, N-well is used to acts the drain of the NMOS. The programmable steps include selecting the anti-fuse by using the NMOS and providing lower power to the un-selected device, higher power biases to the selected device to breakdown the oxide. A further art may refer to the U.S. Pat. No. 6,251,710, entitled “Method of making a dual damascene anti-fuse with via before wire,” assigned to IBM. The drawback of the prior art is that the anti-fuse material too thin about 20 to 150 angstrom and the dielectric is likely loss during the dielectric etching.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating an anti-fuse.
The present invention includes forming a first conductive layer in a first dielectric layer, followed by forming a second dielectric layer on the first dielectric layer. The second dielectric layer is patterned to form openings on the second dielectric layer, a patterned photoresist is used as a mask to etch holes on the bottom of openings through the second dielectric layer to expose the surface of the first conductive layer
4
, then an anti-fuse layer is formed on the second dielectric layer and on a surface of the holes. A photoresist is formed on the anti-fuse layer to expose un-programmable area, followed by plasma etching the anti-fuse layer on the un-programmable area using the photoresist as mask to expose the first conductive layer on the un-programmable area. The photo resist is removed. A second conductive layer is formed on the anti-fuse layer and refilling into the holes. A planarization process is performed by chemical mechanical polishing to polish the second conductive layer to form a programmable anti-fuse.
The anti-fuse layer acts as a barrier to prevent metal atom from diffusion. Preferably, the anti-fuse layer is less than 50 angstroms. The anti-fuse layer comprises SiC, amorphous silicon, and silicon dioxide or silicon nitride.
REFERENCES:
patent: 5447880 (1995-09-01), Lee et al.
patent: 5789764 (1998-08-01), McCollum
patent: 6025226 (2000-02-01), Gambino et al.
patent: 6335228 (2002-01-01), Fuller et al.
patent: 6387792 (2002-05-01), Lehr et al.
patent: 6458631 (2002-10-01), Brintzinger et al.
patent: 2003/0036254 (2003-02-01), Dennison
Cheng Clement
Nguyen Tuan H.
Vanguard International Semiconductor Corp.
LandOfFree
Method for fabricating an anti-fuse in programmable... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating an anti-fuse in programmable..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating an anti-fuse in programmable... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3143737