Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having air-gap dielectric
Reexamination Certificate
2000-01-14
2001-08-21
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having air-gap dielectric
C438S422000, C438S619000
Reexamination Certificate
active
06277705
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88122417, filed Dec. 20, 1999.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device. More particularly, the present invention relates to a method for fabricating an air gap between the interconnects using a hard mask.
2. Description of the Related Art
Advances in the semiconductor technology continuously decrease the semiconductor device dimension into the deep sub-micron territory. As the density of an integrated circuitry increases, the wafer surface becomes insufficient for the manufacturing of the necessary numbers of interconnects. To accommodate the increased number of interconnects, the multi-level metal conductive connect design becomes the approach for Very Large Scale Integration technology.
The continuous decrease in the distance between the metal conductive layers, however, is accompanied by an increase in the aspect ratio of the dielectric layer between the metal conductive layers. The coupling capacitance between the metal conductive layers is thereby increased, leading to the formation of a parasitic capacitance. Parasitic capacitance in a microelectronic device contributes to undesirable effects such as an increase of the RC delay time when electronic signals are
being transmitted between the metal linings. As a result, the speed of the electronic signal transmission between the metal linings is retarded and the operational speed of the semiconductor device is limited.
In order to reduce the transistor-capacitance delay time of the signal transmission, the development of a material with a low dielectric constant k has become the major trend in the semiconductor industry. Currently, materials with a low dielectric constant that are being developed mainly include the spin on polymer (SOP) and the organic spin on glass (OSOG), in which the dielectric constant is approximately between 2 and 4. As the manufacturing of semiconductors enters the deep sub-micron territory, the dielectric layer requires an even lower dielectric constant to accommodate the diminishment of the device dimensions and to improve the performance of the device. Air, having a dielectric constant of close to one and being inexpensive, has become one of the dielectric materials currently under development. If air can be used as a dielectric material, the insulation effect can be highly increased.
SUMMARY OF THE INVENTION
Based on the foregoing, the present invention provides a fabrication method for forming an air-gap using a hard mask. The hard mask layer is used to increase the etching selectivity on the dielectric layer to form an opening with a high aspect ratio. The space occupied by the hard mask layer is further used to form an air-gap after the removal of the hard mask layer.
The present invention provides a fabrication method for forming an air-gap using a hard mask, which method is applicable on a semiconductor substrate. The semiconductor substrate comprises a first conductive layer, for example, a source/drain region of a metal oxide semiconductor (MOS) or a metal interconnect, wherein a dielectric layer is formed on the first conductive layer. The fabrication method according to the present invention includes forming a patterned hard mask layer on the dielectric layer. A portion of the dielectric layer is removed to form an opening in the dielectric layer and to expose the first conductive layer while using the patterned hard mask layer as a mask. A conductive material then fills the opening, forming a conductive plug in the dielectric layer to electrically connect with the first conductive layer. After this, a second conductive layer is formed on the hard mask layer, covering the conductive plug and electrically connecting to the conductive plug. The hard mask layer is then removed, followed by forming a poor step coverage silicon oxide layer, for example, a plasma enhanced silicon oxide layer, to cover the substrate. An air-gap is further formed between the second conductive layer and the dielectric layer to reduce the parasitic capacitance.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
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Charles C. H. Wu & Associates
Gurley Lynne A.
Tsai Jey
United Microelectronics Corp.
Wu Charles C. H.
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