Method for fabricating a very dense chip package

Details Method for fabricating a very dense chip package Method for fabricating a very dense chip package

1998-02-04

2000-07-11

Niebling, John F.

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

438110, H01L 2144, H01L 2148, H01L 2150

Patent

active

060871997

ABSTRACT:
A method for fabricating an integrated circuit package or arrangement includes providing a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having conversely matching bottom surface topographies to permit self-aligned positioning of the chip on the carrier. Chips are provided such that top faces of neighboring chips lie substantially in planes separated by a distance of greater than 0.0 .mu.m. The carrier is arranged and dimensioned such that the neighboring chips are separated by a gap G or spacing in a range of 1 .mu.m<G.ltoreq.100 .mu.m. A metallic interconnect is provided over the top faces and the gap. Preferably, the interconnect has a gradual slope over the gap.

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