Semiconductor device manufacturing: process – Making regenerative-type switching device – Having field effect structure
Reexamination Certificate
2002-01-28
2003-03-04
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making regenerative-type switching device
Having field effect structure
C438S137000, C438S270000
Reexamination Certificate
active
06528355
ABSTRACT:
BACKGROUND OF THE INVENTION
FILED OF THE INVENTION
The invention relates to a method for fabricating a trench MOS (Metal Oxide Semiconductor) transistor in which at least one trench is formed in a semiconductor body. The trench is then at least partly filled with a conductive material which is isolated from the inner surface of the trench by an insulating layer. The insulating layer is introduced into the trench in such a way that it has a larger layer thickness in the region of the lower end of the trench than at the upper end of the trench.
Reducing the on resistance is of major importance when developing new generations of DMOS power transistors. Such a reduction of the on resistance makes it possible to reduce the static power loss and at the same time to achieve higher current densities, so that smaller and cheaper chips can be used for the same total current.
For this reason, for a fairly long time now thought has been given to how the on resistance can be reduced in an expedient manner. In principle, this is possible by departing from a planar cell structure and using trench cells. This is because the use of trench cells makes it possible to reduce the channel resistance of a MOS transistor through a significant enlargement of the channel width per unit area. The resistance of the drift path, which is also referred to as the “epi-resistance” since the drift path is preferably situated in an epitaxial layer applied on a semiconductor substrate, can be reduced by using deep trenches (in this respect cf. U.S. Pat. No. 4,941,026).
However, deep trenches presuppose that a thicker insulating layer, which in this case is also referred to as a field plate, is used in the lower region of the trenches than in the upper region, i.e. in the channel region, with the actual gate oxide.
In the development of trench MOS power transistors, achieving the required gate oxide quality is a particular challenge. On the one hand, the gate oxide must be grown on a wide variety of crystal orientations, because the trench bottom and the edge or corner lying at the surface of the semiconductor body must also be coated with an insulating layer, that is to say the gate oxide. Since the rate of oxide growth depends on the crystal orientation, this leads to an undesired widening of the thickness distribution of the gate oxide over the trench. The oxidation of the curved silicon areas causes thinnings in the gate oxide and peaks in the silicon of the semiconductor body. This in turn adversely affects the electrical quality of the gate oxide, because the thinnest location determines the breakdown field strength. However, the conductive gate material, in particular doped polysilicon, must be guided out at some location via the edge in order to electrically connect the material. The gate oxide is particularly at risk of having a breakthrough at this location.
A further goal in the development of trench MOS power transistors is to modulate the electric field spikes in the off-state case in such a way that the avalanche multiplication occurs in the semiconductor body and not at an interface. This is because the avalanche breakdown at the interface between semiconductor body and gate oxide would lead to the injection of hot charge carriers into the gate oxide and, consequently, a drifting of the component.
The previous methods for fabricating such trench MOS power transistor cells, in which an insulating layer is thicker in the lower region of the trench than in the upper region, are relatively complicated.
One example thereof is described in U.S. Pat. No. 5,326,711. In this known method, by way of example, polycrystalline silicon has to be deposited three times in total in the fabrication process in order to configure the trench in the desired manner.
In a method disclosed in Published European Patent Application No. EP 0 666 590 A2 or in U.S. Pat. No. 5,783,491, the quality of the gate dielectric is improved through the use of two-fold oxidation (“sacrificial oxide”) and etching-away of the oxide. This achieves a certain rounding of the silicon edges.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating a trench MOS power transistor which overcomes the above-mentioned disadvantages of the heretoforeknown methods of this general type and with which it is possible to fabricate a trench with a thicker insulating layer in a lower region than in an upper region in a simple manner.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a trench MOS power transistor, the method includes the steps of:
forming a trench in a semiconductor body;
coating walls and a bottom of the trench with a first insulating film of a given final thickness by applying the first insulating film as a plurality of thermally oxidized and deposited layers;
filling a lower end of the trench with an auxiliary layer;
removing the first insulating film in regions not coated with the auxiliary layer;
removing the auxiliary layer;
growing a second insulating film on uncovered walls at an upper end of the trench such that the second insulating film is thinner than the given final thickness of the first insulating film;
filling the trench at least partly with a conductive material such that the conductive material is insulated from an inner surface of the trench by the first insulating layer and the second insulating layer; and
introducing source zones and body zones into the semiconductor body and providing metallization layers for providing contacting connections.
In other words, in the case of the method for fabricating a trench MOS power transistor, in which at least one trench is introduced into a semiconductor body, which trench is then at least partly filled with a conductive material which is isolated from the inner area of the trench by an insulating layer, the insulating layer being introduced into the trench in such a way that it is provided with a larger layer thickness in the region of the lower end of the trench than at the upper end thereof, the object of the invention is achieved by virtue of the fact that:
(a) the at least one trench is introduced into the semiconductor body,
(b) the walls and the bottom of the trench are coated with a first insulating film, which is formed as a multi-layer system of thermally oxidized and deposited layers;
(c) the lower end of the trench is filled with a first auxiliary layer,
(d) those parts of the first insulating film which are not coated with the first auxiliary layer are removed,
(e) the auxiliary layer is removed,
(f) a second insulating film, which is thinner than the final thickness of the first insulating film, is grown on the uncovered walls of the trench,
(g) the trench is filled with the conductive material, and
(h) source and body zones are introduced into the semiconductor body, and metallization layers are provided for contact connection of these zones.
If the intention is to prevent the removal of the first insulating film in specific regions, which may be the case at the edge, then a further auxiliary layer is applied as masking in these regions. It is also possible to depart from the order specified, for example by making the source and body zones first.
With the method according to the invention, a structure is proposed which both alleviates the critical locations with regard to gate oxide quality and, in the active region, permits modulation of the field distribution through the use of a trench field plate. The actual MOS structure of the transistor with the gate oxide is situated in the upper part of a trench. In the lower part of the trench, the dielectric (field plate) is thicker than the gate oxide. As a result, a higher voltage can be dropped across the dielectric, which permits deeper trenches and a lower on resistance Ron. The transition between gate oxide and field plate oxide is preferably graduated. An abrupt transition would lead to unfavorable field spikes in the silicon. The trenches can be provided both in cells and strips and in any other
Hirler Franz
Kotek Manfred
Larik Joost
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Nguyen Tuan H.
Stemer Werner H.
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