Semiconductor device manufacturing: process – Making passive device – Trench capacitor
Reexamination Certificate
2002-09-04
2004-05-11
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making passive device
Trench capacitor
C438S397000, C438S398000
Reexamination Certificate
active
06734077
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for fabricating a trench capacitor for a semiconductor memory.
Semiconductor memories, such as, for example, Dynamic Random Access Memories (DRAMs), include a cell array and driving peripherals. Memory cells are disposed in the cell array.
The cell array of a DRAM chip includes a matrix of memory cells disposed in the form of rows and columns and driven by word lines and bit lines. The reading of data from the memory cells or the writing of data to the memory cells is effected by the activation of suitable word lines and bit lines.
A memory cell of a DRAM usually includes a transistor that is connected to a capacitor. The transistor includes, inter alia, two doping regions that are separated from one another by a channel that is controlled by a gate. One doping region is referred to as a drain region and the other doping region is referred to as a source region.
One of the doping regions is connected to a bit line and the other of the doping regions is connected to a capacitor. The gate is connected to a word line. Applying suitable voltages to the gate controls the transistor such that a flow of current between the doping regions through the channel is switched on and off.
The integration density is increased by the ongoing miniaturization of memory components. The increase in the integration density means that the area that is available for each memory cell is constantly decreasing. Accordingly, the selection transistor and the storage capacitor of a memory cell are subject to a constant reduction in their geometric dimensions.
The ongoing attempts to reduce the size of the memory devices promote the construction of DRAMs with a high density and smaller characteristic size, i.e., smaller area per memory cell. Smaller components, such as, for example, smaller capacitors, are used to fabricate memory cells that require less surface area. The use of smaller capacitors, however, results in a lower storage capacitance on the part of the individual capacitor, which, in turn, may have an adverse effect on the operating ability and usability of the memory device.
By way of example, read amplifiers require a sufficient signal level to reliably read out the information that is stored in the memory cells. The ratio of the storage capacitance to the bit line capacitance is crucial in determining a sufficient signal level. If the storage capacitance is too low, the ratio may be too small to generate a sufficient signal to drive the read amplifier. Likewise, a lower storage capacitance requires a higher refresh frequency.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating a trench capacitor for a semiconductor memory that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that increases the surface area of the electrodes of the trench capacitor.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method for fabricating a trench capacitor for a semiconductor memory, including the steps of providing a substrate having a substrate surface, forming at least one trench in the substrate surface, the trench having an upper region, a lower region, and a trench sidewall, introducing dopant through the trench sidewall in the lower region of the trench to form an outer capacitor electrode from a buried doping layer, forming a masking layer on the trench sidewall of the lower region of the trench, depositing nanocrystallites on the masking layer covering a first part of the masking layer and leaving clear a second part of the masking layer, etching the masking layer to uncover the trench sidewall with the nanocrystallites serving as an etching mask, the masking layer covered by the nanocrystallites remaining as a patterned mask layer on the trench sidewall, etching the substrate in the lower region of the trench utilizing the patterned mask layer to form microtrenches in the substrate and to roughen the trench sidewall, removing the patterned mask layer with an etch, forming an insulation layer on the roughened trench sidewall, depositing a conductive trench filling in the trench on the insulation layer as an inner capacitor electrode, and forming a selection transistor connected to the conductive trench filling to drive the trench capacitor.
With regard to the method, fabrication of a trench capacitor for a semiconductor memory includes the steps of:
providing a substrate having a substrate surface in which a trench, which has an upper region, a lower region, and a trench sidewall, is formed,
introducing dopant through the trench sidewall in the lower region of the trench, a buried doping layer of increased dopant concentration being formed as an outer capacitor electrode;
forming a masking layer on the trench sidewall of the lower region of the trench;
depositing nanocrystallites on the masking layer so that the nanocrystallites cover a first part of the masking layer and leave clear a second part of the masking layer;
etching the masking layer, during which the trench sidewall is uncovered, the nanocrystallites serve as an etching mask, and the mask layer that is covered by the nanocrystallites remains as a patterned mask layer on the trench sidewall;
etching the substrate in the lower region of the trench using the patterned mask layer, during which microtrenches are formed in the substrate and a roughened trench sidewall is produced;
removing the patterned mask layer by an etch;
forming an insulation layer on the roughened trench sidewall;
depositing a conductive trench filling in the trenches on the insulation layer as an inner capacitor electrode; and
forming a selection transistor that is connected to the conductive trench filling to drive the trench capacitor.
The method according to the invention roughens the trench sidewall in the lower region of the trench so that the surface area of the outer capacitor electrode of the trench capacitor is increased in size. According to the invention, for such a purpose, a mask layer is applied in the lower region of the trench and is patterned by deposited nanocrystallites. The patterned mask layer is then used as an etching mask for the etching of the trench sidewall in the lower region of the trench. Microtrenches are etched into the trench sidewall or substrate. The microtrenches in the substrate increase the surface area of the outer capacitor electrode. The enlarged outer capacitor electrode then allows a higher capacitance to be achieved in the trench capacitor or a constant capacitance to be achieved in the trench capacitor even when the geometric dimensions of the trench capacitor are reduced, for example, the surface area required at the substrate surface of the trench capacitor.
A trench capacitor that has been fabricated using the method has microtrenches in the trench sidewall of the lower region of the trench. The microtrenches are formed in the substrate, which is in single crystal form, and are used to increase the surface area of the outer capacitor electrode. The outer capacitor electrode is formed as a buried doping layer around the lower region of the trench, in the single-crystal substrate, as a highly doped layer. The enlarged surface area of the outer capacitor electrode makes it possible to achieve a higher capacitance for the trench capacitor according to the invention. As a result, the trench capacitor allows reliable operation of a memory cell. Increasing the size of the capacitor electrode by roughening also makes it possible to reduce the amount of the substrate surface area that is taken up by the trench capacitor as a result of the diameter of the trench being reduced, the trench capacitor in the trench retaining the same level of capacitance on account of the roughened outer capacitor electrode.
In accordance with another mode of the invention, an insulation collar is produced in the upper region of the trench, on the trench sidewall of the trench, before the trench sidewall is rou
Förster Matthias
Moll Anett
Morgenschweis Anja
Sachse Jens-Uwe
Schupke Kristin
Duong Khanh
Infineon - Technologies AG
Mayback Gregory L.
Trinh Michael
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