Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Thinning of semiconductor substrate
Reexamination Certificate
2001-10-04
2003-02-18
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Thinning of semiconductor substrate
C438S977000, C438S751000
Reexamination Certificate
active
06521512
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates in general to a method of fabricating three-dimensionally integrated circuits. In particular, the invention relates to a method of fabricating a thin, free-standing semiconductor device layer, in which a plurality of via holes extend from the devices and/or from metallisation layers to a surface of the thin, free-standing semiconductor device layer. The free-standing semiconductor device layer and individual chips obtained therefrom are then used to fabricate a three-dimensionally integrated circuit.
Three-dimensional integration, i.e. vertical interconnection of devices fabricated by planar technology is becoming increasingly important as higher package densities and switching rates may be obtained as compared to two-dimensional systems. Current methods available in practice or in the literature for vertical interconnection for very large scale integrated (VLSI) devices are, however, relatively complex. The VLSI chips must have some through-wafer structures for vertical (backside) interconnect and backside contact and must be thinned to an appropriate thickness for good electrical performance (low vertical interconnect resistance) and good thermal control (minimal thermal mass of the stacked silicon). The final thickness of the vertically integrated chips is also important in end products where total IC volume and not just density in x and y is a key differentiator such as in hand held and mobile applications.
In a first step of a method for making a three-dimensionally integrated circuit, it is necessary to fabricate thin chips containing fully processed semiconductor devices and interconnection openings leading from the devices to one surface of the thin chips. There are methods in the literature or available from vendors for thinning wafers after full integration. For example, the methods as proposed by the company Tru-Si Technologies (see literature and advertisements from Tru-Si Technologies, an equipment vendor) involve grinding and a special type of plasma etch for the thinning of the entire wafer. The special plasma etch has a relatively slow etch rate and the equipment is relatively expensive.
Finally, wafers thinner than 300 &mgr;m (for 200 mm wafers) start to present major handling challenges due to bowing. However, in the three-dimensionally stacked chip application, the final thickness should be under 100 &mgr;m and preferably no thicker than required by the depths of the junctions plus the required thickness of underlying substrate required for the active circuits to be stacked. For example, for a 64M DRAM with deep trench capacitors and with metal-, metal silicide- or doped polysilicon-filled trenches as a vertical interconnect, the thickness of the finished chip for 3-D integration should be in the range of 15-20 &mgr;m. The thickness of the chip determines the length of the vertical interconnect. Thicker chips therefore result in increased difficulty in processing and filling the interconnect via holes and an increased resistance of the vertical interconnects. However, for VLSI devices without these trench capacitors or deep junctions, the chips could be thinner and the vertical interconnects easier to be processed.
It is quite difficult to thin a starting wafer from its initially full thickness (approximately 750 &mgr;m for 200 mm wafers) to <100 &mgr;m with good uniformity and without damage. U.S. Pat. No. 5,563,084, which is incorporated herein by reference, discloses a method of making a three-dimensional integrated circuit. The method includes providing a first substrate that at a first surface is provided with at least one fully processed device plane containing a plurality of independent devices or circuits in a side-by-side configuration, wherein the devices or circuits of a plurality of device planes form a device stack. A second substrate is provided which at one surface is provided with at least one fully processed device plane containing a plurality of independent devices or circuits in a side-by-side configuration, wherein the devices and circuits of a plurality of device planes form a device stack. The devices, the device stacks or the circuits having been tested to distinguish between functioning and defective devices, device stacks or circuits. One surface of the second substrate is connected to an auxiliary substrate. The second substrate is thinned or reduced from a surface opposite the main surface. The auxiliary substrate and the devices connected thereto are separated into individual chips respectively containing functioning or defective devices, device stacks or circuits. The chips containing the functioning devices, the device stacks or the circuits are aligned and attached in a side-by-side relationship on the first side of the first substrate and the auxiliary substrate is then removed. The moats created between individual chips as a result of their aligning and attaching are planarized and simultaneously with, or subsequently to, the attaching of the chips, providing electrical contacts between the devices, the device stacks or the circuits of the attached chips and the devices, device stacks and circuits of the first substrate. In a preferred embodiment, the second device substrate is shown to be made from a normal silicon wafer. It is also disclosed that the second substrate can be made of a silicon-on-insulator (SOI) substrate. In this case, it is mentioned that when thinning or reducing the second substrate instead of thinning the upper substrate down to close to the device layers, the substrate below the oxide layer of the SOI substrate may be removed.
A similar method is disclosed in German Patent DE 198 13 239 C1. It also states that the substrate to be reduced and thinned may be an SOI substrate. Moreover, it teaches that before thinning of the substrate the via holes should be formed through the oxide layer and the thinning of the substrate should be terminated when the oxide layer is reached.
The methods as disclosed in the two aforementioned patents are disadvantageous as the via holes and thus the vertical interconnections are relatively long as they must be formed through the device layer and the oxide layer formed under the device layer. It is therefore difficult to fabricate vertical interconnects which contain a sufficiently low resistance to electrically connect devices in adjacent device planes. Moreover, due to the length and aspect ratio of the via holes in the state of the art, it is difficult to deposit the electrically conducting material in a reliable manner.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating a thin, free-standing semiconductor device layer and for making a three-dimensionally integrated circuit which overcomes the above-mentioned disadvantages of the prior art method devices of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a thin, free-standing device semiconductor layer. The method includes providing a semiconductor specimen having a semiconductor substrate, a buried insulation layer formed in the semiconductor substrate, and a semiconductor device layer disposed on the buried insulation layer and defining a first surface of the semiconductor specimen. The semiconductor device layer has a plurality of independent devices and metallization layers disposed therein. The semiconductor substrate extends from the buried insulation layer to a second surface of the semiconductor specimen opposite the first surface. The semiconductor device layer has a plurality of via holes formed therein and each extends to the buried insulation layer from one of the independent devices and the metallization layers. A thickness of the semiconductor substrate is reduced from the second surface by performing the steps of etching the semiconductor substrate down to the buried insulation layer with the buried insulation layer functioning as an etch stop layer; and etching the buried insu
Chaudhari Chandra
Hogans David
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