Method for fabricating a sub-half micron MOSFET device with insu

Details Method for fabricating a sub-half micron MOSFET device with insu Method for fabricating a sub-half micron MOSFET device with insu

1996-08-26

1997-11-25

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 67, 437229, H01L 21762

Patent

active

056912153

ABSTRACT:
A process for globally planarizing the insulator used to fill narrow and wide shallow trenches, used in a MOSFET device, structure, has been developed. The process features smoothing the topography that exists after the insulator filling of narrow and shallow trenches, by creating photoresist plugs, only in the depressed topography regions. This is accomplished using a negative photoresist layer, a de-focus exposure, and the identical mask used to create the shallow trench pattern in a positive photoresist layer. A RIE procedure, with a 1:1 etch selectivity, is used to complete the planarization process.

REFERENCES:
patent: 4506434 (1985-03-01), Ogawo et al.
patent: 4836885 (1989-06-01), Breiten et al.
patent: 4916087 (1990-04-01), Tateoka et al.
patent: 5077234 (1991-12-01), Scoopo et al.
patent: 5175122 (1992-12-01), Wang et al.

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