Method for fabricating a stacked capacitor with a self aligned n

Details Method for fabricating a stacked capacitor with a self aligned n Method for fabricating a stacked capacitor with a self aligned n

1996-02-02

1996-09-10

Tsai, H. Jey

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170, H01L 2700

Patent

active

055545572

ABSTRACT:
The present invention provides a method of manufacturing a fence shaped capacitor for a DRAM which begins by providing a substrate including a field effect transistor having a transfer gate with nitride sidewall spacers. Next, a first insulation layer, a first polysilicon layer and a second insulation layer are formed over the transistor. A patterning step is used to define first openings in the second insulation layer over the source of the transistor. First polysilicon sidewall spacers (e.g., fences) are formed on the sidewalls of the first opening thus defining a second opening. Using the first spacers and the spacers on the transfer gates, the first insulation layer is etched to expose the source and thereby forming a node contact opening. A bottom storage electrode is formed covering the first spacers (e.g., fences) and the sidewall of the node contact opening. A dielectric layer and top plate electrode are formed over the bottom storage electrode. The method reduces process complexity by using only one photo operation to form the node contact opening and increases process tolerances by making the node contact self-aligning using the first sidewall spacers and the nitride sidewall spacers.

REFERENCES:
patent: 5164881 (1992-11-01), Ahn
patent: 5185282 (1993-02-01), Lee et al.
patent: 5234855 (1993-08-01), Rhodes et al.
patent: 5380673 (1995-01-01), Yang et al.
patent: 5409855 (1995-04-01), Jun
patent: 5444010 (1995-08-01), Park et al.

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