Method for fabricating a solid electrolyte memory device and...

Metal working – Barrier layer or semiconductor device making – Barrier layer device making

Reexamination Certificate

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C438S396000, C257SE21008

Reexamination Certificate

active

07658773

ABSTRACT:
A method for fabricating a solid electrolyte memory device comprises a plurality of solid electrolyte memory cells, the solid electrolyte memory cells sharing a common continuous solid electrolyte layer comprising solid electrolyte cell areas and solid electrolyte inter-cell areas, the method comprising the process of introducing mobile ion solubility reducing material or mobile ion mobility reducing material into the solid electrolyte inter-cell areas.

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patent: 10 2005 001 253 (2006-07-01), None
Kozicki, M.N., et al., “Can Solid State Electrochemistry Eliminate the Memory Scaling Quandary?,” IEEE Silicon Nanoelectronics Workshop, 2002, 15 pages.
Symanczyk, R., et al., “Electrical Characterization of Solid State Ionic Memory Elelments,” NVMTS, 2003, 6 pages.
Kund, M., et al., “Conductive bridging RAM (CBRAM): An emerging non-volatile memory technology scalable to sub 20nm,” IEEE, 2005, Session 31.5, 4 pages.

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