Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Encapsulating
Reexamination Certificate
2000-03-30
2002-09-03
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Encapsulating
C438S113000, C438S613000
Reexamination Certificate
active
06444499
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the packaging electronic components. More particularly, the present invention relates to the fabrication of a plurality of packaged electronic components on a single substrate.
BACKGROUND OF THE INVENTION
Virtually every business in the world has become dependent, directly or indirectly, on electronic components such as integrated circuits. In addition, electronic components have permeated our personal lives through their use in systems that control or contribute to almost every aspect of our day from coffee making to network computing. This application of electronic components to what were once seemingly unrelated fields has created a huge demand for these components in increasingly diverse industries and locations. Consequently, there has been a corresponding increase in demand for better methods and structures to package electronic components. This demand has made electronic component packaging one of the most critical and competitive markets in the electronics industry.
To stay competitive, those of skill in the art of electronic component packaging are constantly seeking better ways to provide protection of the extremely fragile electronic components from environmental elements and contamination while, at the same time, providing a solution which does not significantly increase the cost of the finished, packaged electronic component to the system manufacturer or the consumer. In one effort to reduce the cost of individual packaged electronic components, those of skill in the art have developed prior art methods and structures that allow electronic component packaging companies to fabricate multiple packaged electronic components from a single substrate, i.e., multiple packaged electronic components are created at once using a single substrate.
FIG. 1A
is an enlarged top plan view of a prior art multi-package array substrate
13
. Prior art multi-package array substrate
13
is one of several types of prior art substrates such as the prior art substrate discussed in U.S. Pat. No. 5,981,314 entitled “Near Chip Size Integrated Circuit Package”, issued Nov. 9, 1999 to Thomas Glen, Roy Hollaway and Anthony Panczak, and assigned to the assignee of the present invention, which is incorporated in its entirety herein. In
FIG. 1A
, a plurality of lines
56
oriented in the vertical direction, as well as a plurality of lines
58
oriented in the horizontal direction are illustrated. Lines
56
and
58
were included to define the sections
12
where each individual packaged electronic component is to be formed. (For clarity, in
FIG. 1A
only two sections
12
are labeled). As shown in
FIG. 1A
, the periphery of each section
12
is defined by lines
56
,
58
. However, in an alternative embodiment, instead of lines
56
,
58
, alignment marks and/or fiducials were provided for aligning prior art multi-package array substrate
13
in subsequent processing steps discussed below. Consequently, in some prior art embodiments lines
56
and
58
were not solid lines. In addition, even when lines
56
and
58
were solid lines, lines
56
and
58
were typically only marks on a first surface
18
of prior art multi-package array substrate
13
.
As shown in FIG.
1
A and
FIG. 1B
, a dam
59
is typically formed on a first surface
18
of prior art multi-package array substrate
13
, around the perimeter of prior art multi-package array substrate
13
. Dam
59
encloses sections
12
, yet does not extend into any of the sections
12
.
FIG. 1B
is a cross-sectional view along the line IB—IB of
FIG. 1A
of prior art multi-package array substrate
13
. In practice, prior art multi-package array substrate
13
would also include conductive through-holes and other features which are not illustrated in
FIG. 1B
for clarity. As shown in
FIG. 1B
, dam
59
extends from first surface
18
to a predetermined height indicated by dashed line
68
above first surface
18
thereby defining a pocket which can be filled with encapsulant as described in more detail below.
Referring back to
FIG. 1A
, each section
12
of prior art multi-package array substrate
13
typically has a plurality of metallizations
22
formed on first surface
18
of prior art multi-package array substrate
13
. In addition, a plurality of contacts (not shown) formed on metallizations
22
and a plurality of conductive through-holes (not shown) formed through prior art multi-package array substrate
13
could also be included but are not shown in FIG.
1
A and
FIG. 1B
for simplicity and to avoid detracting from the discussion at hand.
Metallizations
22
are typically formed using conventional techniques such as by forming a conductive layer on first surface
18
and then by masking and etching the conductive layer. Conductive through-holes (not shown in FIG.
1
A and
FIG. 1B
) can also be formed using conventional techniques such as by drilling through-holes in prior art multi-package array substrate
13
and then plating the drilled through-holes with a conductive metal such as copper.
FIGS. 2A and 2B
are cross-sectional and top plan views, respectively, of an exemplary section
12
of substrate
13
(
FIG. 1A
) further along in processing. As shown in
FIG. 2A
, a first surface
32
of an electronic component such as an integrated circuit (IC) chip
30
is typically mounted to first surface
18
of prior art multi-package array substrate
13
by a layer of adhesive
34
. As shown in
FIG. 2B
, IC chip
30
is typically mounted to section
12
in a location central to metallizations
22
. Also shown are bonding pads
38
located on a second surface
36
of IC chip
30
. Bonding pads
38
are typically electrically connected to corresponding contacts
23
by bond wires
40
, made of gold or aluminum for example, using conventional wire bonding techniques.
In an alternative prior art embodiment (not shown) instead of mounting first surface
32
of IC chip
30
to first surface
18
of prior art multi-package array substrate
13
and electrically connecting bonding pads
38
to contacts
23
and metallizations
22
using bond wires
40
as illustrated in
FIGS. 2A and 2B
, IC chip
30
is mounted to substrate
13
using a flip chip interconnection. In this prior art embodiment (not shown), second surface
36
of IC chip
30
is placed adjacent first surface
18
of substrate
13
and bonding pads
38
are electrically connected to contacts
23
and metallizations
22
directly, for example, by solder. An under fill material is then applied to fill the space between IC chip
30
and substrate
12
and also to encapsulate the flip chip interconnection between bonding pads
38
and metallizations
22
.
FIG. 2C
is a cross-sectional view of an exemplary section
12
further along in processing. As shown in
FIG. 2C
, a layer of encapsulant
42
is applied over the entire assembly. In particular, layer of encapsulant
42
covers IC chip
30
including bonding pads
38
, bond wires
40
, contacts
23
, metallizations
22
and the remaining exposed first surface
18
of prior art multi-package substrate
13
. Typically, layer of encapsulant
42
is formed of an electrically insulating encapsulant and can be laser marked for product identification using conventional laser marking techniques. Layer of encapsulant
42
is typically applied as a liquid and then dries, or is cured, to a hardened solid.
Referring back to
FIGS. 1A and 1B
, and in particular to
FIG. 1B
, layer of encapsulant
42
is applied by filling the pocket defined by dam
59
with encapsulant. Dam
59
prevents layer of encapsulant
42
from flowing off first surface
18
of prior art multi-package substrate
13
. Typically, dam
59
has a height indicated by dashed line
68
above first surface
18
greater than or equal to the height of upper surface
48
of layer of encapsulant
42
(
FIG. 2C
) above first surface
18
.
As also shown in
FIG. 2C
, interconnection balls
28
, typically eutectic solder balls, are attached to contacts
27
using conventional techniques.
FIG. 2D
is a bottom pl
Glenn Thomas P.
Swiss Gary L.
Amkor Technology Inc.
Fahmy Wael
Gunnison McKay & Hodgson, L.L.P.
Kebede Brook
McKay Philips J.
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