Semiconductor device manufacturing: process – Making passive device – Planar capacitor
Patent
1998-02-02
2000-05-23
Nguyen, Tuan H.
Semiconductor device manufacturing: process
Making passive device
Planar capacitor
438394, 438251, H01L 2120
Patent
active
060665378
ABSTRACT:
A multilevel capacitor structure compatible with CMOS processing for use in switched capacitor circuits is disclosed. The capacitor structure has an associated parasitic capacitor which is placed in such a way so as to minimize the impact on the performance of a the switched capacitor circuit. The parasitic capacitor is formed between a first plate of the shielded capacitor and a diffusion well within a substrate. The diffusion well is connected to a quiet voltage reference source to isolate the shielded capacitor from noise present on the substrate. The shielded capacitor has a first plate that is fabricated from a first conductive material such as polycrystalline silicon or polycide, a second plate fabricated from a second conductive material such as a first level of metal on an integrated circuit, and a third capacitor plate fabricated from a second level of metal of an integrated circuit. The first plate and the third plate are connected to give a total capacitance given by the sum of capacitances between the first plate and second plate and between the second plate and third plate.
REFERENCES:
patent: 4700457 (1987-10-01), Matsukawa
patent: 4914456 (1990-04-01), Alter
patent: 5021920 (1991-06-01), Smith
patent: 5077225 (1991-12-01), Lee
patent: 5166858 (1992-11-01), Frake et al.
patent: 5220483 (1993-06-01), Scott
patent: 5589416 (1996-12-01), Chittipeddi
patent: 5874770 (1999-02-01), Saia et al.
Analog MOS Integrated Circuits for Signal Processing, G. Temes & R. Gregorian, John Wiley & Sons, United States of America, 1996, pp. 514-519.
Ackerman Stephen B.
Knowles Billy
Nguyen Tuan H.
Saile George O.
Tritech Microelectronics Ltd.
LandOfFree
Method for fabricating a shielded multilevel integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating a shielded multilevel integrated circuit , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating a shielded multilevel integrated circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1836593