Method for fabricating a shallow trench isolation structure

Details Method for fabricating a shallow trench isolation structure Method for fabricating a shallow trench isolation structure

1998-09-14

2001-02-20

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S221000, C438S296000, C438S692000

Reexamination Certificate

active

06190999

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87109988, filed Jun. 22, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method for fabricating a STI structure to prevent microscratch from occurring on the STI structure during a chemical mechanical polishing (CMP) process.
2. Description of Related Art
The purpose of an isolation structure in an IC device is to prevent carriers, such as electrons or electron-holes, from drifting between two adjacent device elements through a semiconductor substrate to cause a current leakage. For example, carriers drift between two adjacent transistor through their substrate. Conventionally, isolation structures are formed between field effect transistors (FETs) in an IC device, such as a dynamic random access memory (DRAM) device, to prevent a current leakage from occurring. A shallow trench isolation (STI) structure is one of the isolation structures being widely used.
FIGS. 1A-1D
are cross-sectional views of a semiconductor device schematically illustrating a conventional fabrication process for forming a shallow trench isolation structure. In
FIG. 1A
, a pad oxide layer
102
and a silicon nitride layer
104
are sequentially formed over a semiconductor substrate
100
. In
FIG. 1B
, a trench
106
is formed in the substrate
100
by patterning over the substrate
100
through, for example, photolithography and etching. The silicon nitride layer
104
and the pad oxide layer
102
are etched through and become a silicon nitride layer
104
a
and a pad oxide layer
102
a
. Then, a liner oxide layer
108
is formed over the side-wall of the trench
106
.
In FIG.
1
C and
FIG. 1D
, an oxide layer
110
is formed over the substrate
100
so that the trench
106
shown in
FIG. 1B
is filled with oxide. A CMP process is, for example, performed to polish the oxide layer
110
, in which the silicon nitride layer
104
a
is used as a polishing step so that it is exposed. Then, the silicon nitride layer
104
a
is removed by, for example, wet etching. A residual of the oxide layer
110
fills the trench
106
becoming a STI oxide
110
a.
The CMP process is one of planarization technologies by making use of slurry, which is a chemical reagent, to chemically and mechanically polish the uneven surface of a deposited oxide layer so as to achieve a planarization purpose. Slurry contains a huge number of fine grinding particles with a dimension of about 0.1-0.2 microns. The grinding particles compose a good abrasive. A rotating holder holds the wafer on the backside. The front surface is pushed onto a polishing pad, which is held by a rotating polishing table. Slurry is provided on the contact surface between the polishing pad and the front surface of the wafer. Since they are rotated, the polishing purpose is achieved. The ingredient of slurry is different for a different material to be polished.
During the CMP process, the fine grinding particles may cause a microscratch on a soft material. For example, in a method for fabricating a STI structure as described above, the oxide layer
110
is usually formed by atmospheric pressure (AP) chemical vapor deposition (CVD) (APCVD). In
FIG. 1C
, the oxide layer
110
is thereby soft. As the CMP process is performed to form the STI oxide
110
a
, in order to totally remove the oxide layer
110
above the silicon nitride layer
104
a
, the silicon nitride layer
104
a
is strategically over-polished. Since the hardness of silicon nitride is higher than oxide, oxide is polished away with a higher rate to cause a dishing top surface of the STI oxide
110
a
. The dishing phenomenon affects the performance of the device.
Moreover, during the over-polishing stage, the CMP process polishes silicon nitride to produce silicon nitride particles, which are mixed with slurry and cause a damage on the STI oxide
110
a
, such as a microscratch
112
. Even though the microscratch phenomenon is not observable by eye, if it is not fixed, it may cause an occurrence of a bridge between polysilicon gates formed subsequently or an occurrence of pattern distortion, in which the bridge may induce current leakage. The microscratch phenomenon then results in a failure of device. The yield rate is decreased.
Furthermore, since the silicon nitride layer
104
a
is not removed before forming the oxide layer
110
, the total depth of the trench
106
counting from the silicon nitride layer
104
a
is large. This deteriorates the filling performance of the oxide layer
110
into the trench
106
.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method for fabricating a STI structure with a prevention of microscratch resulting from performing a CMP process on it.
It is another an objective of the present invention to provide a method for fabricating a STI structure, which has smaller trench depth so as to increase the filling performance into the trench.
It is still another an objective of the present invention to provide a method for fabricating a STI structure that avoids a dishing phenomenon often due to an over-polishing process.
In accordance with the foregoing and other objectives of the present invention, a method is provided for fabricating a STI structure having a pad oxide layer and a hard masking layer that are sequentially formed over a semiconductor substrate. In accordance with the method, a trench is formed in the substrate by patterning over the substrate. Then, the hard masking layer is removed to expose the pad oxide layer. An insulating layer is formed over the substrate to fill the trench. Using the pad oxide layer as a polishing stop, a CMP process is performed to polish the insulating layer until the pad oxide layer is exposed. The remained pad oxide within the trench is simultaneously planarized to have the same height as the height of the pad oxide layer. After the pad oxide is removed, the STI structure is accomplished.


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