Method for fabricating a shallow trench isolation

Details Method for fabricating a shallow trench isolation Method for fabricating a shallow trench isolation

1998-09-14

2000-10-17

Bowers, Charles

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438221, 438359, H01L 2176

Patent

active

061331147

ABSTRACT:
A method for fabricating a STI structure includes a pad oxide layer and a hard masking layer are sequentially formed over a semiconductor substrate. A trench is formed in the substrate by patterning over the substrate. A liner oxide layer is formed over a side-wall of the trench in the substrate. An isolating layer by APCVD and an isolating layer by HDPCVD are sequentially formed over the substrate, in which the height of the CVD isolating layer within the trench is lower than the height of the hard masking layer. A CMP process is performed, using the hard masking layer as a polishing stop. The hard masking layer and the pad oxide layer are removed to accomplish the STI structure.

REFERENCES:
patent: 5728621 (1998-03-01), Zheng et al.
patent: 5817567 (1998-10-01), Jang
patent: 5918131 (1999-06-01), Hsu et al.
patent: 5998278 (1999-12-01), Yu
patent: 6017803 (2000-01-01), Wong

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