Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-09-27
2001-06-12
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S430000, C438S275000, C438S700000
Reexamination Certificate
active
06245640
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a method for fabricating a semiconductor structure in an integrated circuit, in particular a method for fabricating a hard mask and a method for removing the hard mask.
Silicon oxides are among the most frequently used materials in semiconductor technology. Various types of silicon oxides (glasses) are known which differ in terms of their composition, their properties and their fabrication, for example thermal and deposited oxides, TEOS, and doped oxides. They are used as insulation materials in many cases. A further important application is their use as a hard mask during the etching of layers lying at a deeper level. A hard mask of this type is removed again after the etching process.
A photolithographic process is required to produce the hard mask. In order to reduce pattern transfer errors in the course of this, it is possible to apply an antireflection layer (ARC) to the hard mask layer, for which purpose a plasma-enhanced deposition process is usually used. Customary methods provide for the hard mask layer composed of a silicon oxide to be applied in the vacuum chamber of a first installation and for the antireflection layer then to be applied in a second installation.
After the patterning process, the hard mask composed of silicon oxide should be removed wet-chemically as quickly as possible and usually selectively with respect to other layers that are present (for example thermal silicon oxide layers and silicon nitride layers). This requires a high, numerically accurately known etching rate for the hard mask. As a result of the effect of the plasma-enhanced deposition process for the antireflection layer on the exposed silicon oxide layer, however, the etching rate of the latter is reduced in an uncontrolled manner. The change in the etching rate can be attributed to chemical and physical layer modifications due to the subsequent plasma deposition. Since the etching rate of the hard mask layer cannot adequately be controlled, under manufacturing conditions the hard mask is not removed with a fixed process time, rather the process time is determined in a separate precursor test for a certain number of wafers (that is to say a batch). An individual etching time is established in this way for each batch. It is only by this time-consuming and cost-intensive procedure that an excessively high erosion of other layers present on the wafer can be avoided.
One example of the use of a hard mask made of doped silicon oxide with a superior antireflection layer is the etching of capacitor trenches in a silicon substrate, in particular for one-transistor memory cells. In the case of the etching process, an intermediate layer composed of thermal silicon oxide and/or silicon nitride is generally disposed directly on the substrate surface and must not be attacked, or may be attacked only slightly, during the removal of the hard mask after the trench etching. It may be expedient to etch the intermediate layer back horizontally by a defined amount (so-called pull back), for example in order to enable the trench to be better able to be filled. According to a known method, in order to remove the silicon oxide-based hard mask layers, mixtures containing H
2
SO
4
/HF are used here at approximately 60° C on a spin etcher. The selectivity of the erosion of a doped glass layer with 4% by weight of boron with respect to the erosion of a thermal silicon oxide layer that is likewise situated on the wafer is approximately 35:1 in this case. In order to prevent an impermissibly high erosion of the thermal oxide, from each batch one wafer is subjected separately to a preliminary process step for determining the etching rate. The entire batch is subsequently processed with the etching time resulting from the etching rate that has been determined in this way. This step preceding the actual etching process considerably reduces the wafer throughput. After the removal of the hard mask, in a further process step, the edges of the silicon nitride layer situated under the hard mask are etched back by isotropic etching using an HF/ethylene glycol mixture in another etching installation.
It is known to increase the wet etching rate of doped silicon oxide hard masks by increasing the dopant concentration of the layers. However, this reduces their layer stability in the etching process, that is to say the layers no longer satisfy the requirements Appertaining to their use as a mask.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating a semiconductor structure, which overcomes the above-mentioned disadvantages of the prior art methods of this general type.
With the foregoing and other objects in view there is provided, in accordance w-th the invention, a method for fabricating a semiconductor structure, which includes depositing a doped silicon oxide layer on a support in a first CVD step; depositing an antireflection layer on the doped silicon oxide layer in a plasma-assisted second CVD step with no interruption of vacuum conditions for the support between the first CVD step and the plasma-assisted second CVD step; patterning of the doped silicon oxide layer and of the antireflection layer for forming a mask; etching the support using the mask; removing the antireflection layer; and removing the doped silicon oxide layer using an etching solution containing at least one of HF and ethylene glycol and sulfuric acid.
The invention is based on the problem of specifying a method for fabricating the stable hard mask, composed of silicon oxide, and the antireflection layer lying above it, and also of specifying an etching method which enables the silicon oxide hard mask to be removed at a high etching rate. The etching method is intended to have a high selectivity, and if appropriate a selectivity that is adjustable in a defined manner, with respect to other layers, in particular with respect to an intermediate layer made of thermal silicon oxide and/or silicon nitride.
The method according to the invention is based on applying a hard mask layer composed of a doped silicon oxide and an antireflection layer successively with no interruption of the vacuum conditions for the wafer by plasma-enhanced deposition processes. The invention is also based on using a mixture of HF and ethylene glycol (EG) and/or sulfuric acid for the removal of the hard mask, which mixture, for the hard mask thus fabricated, has both a high etching rate and a high and defined selectivity with respect to further layers possibly present on the substrate.
As a result of the “in situ” application of the antireflection layer to the silicon oxide layer, the direct effect of the surrounding atmosphere on the silicon oxide layer is reduced and the absorption of moisture is distinctly reduced. This results in a higher etching rate for the silicon oxide layer.
At the same time, a higher deposition rate is obtained during the fabrication of the antireflection layer, with the result that the deposition can be effected in a shorter time and the exposure of the hard mask layer to plasma is reduced. This results in less modification of the layer properties and a higher etching rate for the hard mask.
A doped glass containing from 2 to 9% by weight of B and/or 2 to 9% by weight of P is preferably used as the hard mask layer. In this case, a boron concentration of from 3.5 to 4% without the addition of phosphorus is particularly referred, since such a doped glass layer (BSG) has particularly good hard mask properties. A customary ozone-assisted SA (sub-atmosphere) CVD process can be used for fabricating the layer. In particular if a heavily doped layer (≧4% by weight of B) is used, an inert plasma step can be carried out before the deposition of the antireflection layer, the step serving for strengthening the BSG layer and no layer deposition being effected in the step. The inert plasma step can be adapted to the specific requirements, by altering the plasma power and the process time, to the effect that it is possible to fulfill
Claussen Wilhelm
Lorenz Barbara
Penner Klaus
Sperlich Hans-Peter
Vogt Mirko
Greenberg Laurence A.
Lerner Herbert L.
Pham Long
Siemens Aktiengesellschaft
Stemer Werner H.
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