Metal treatment – Compositions – Heat treating
Patent
1980-11-07
1982-10-26
Roy, Upendra
Metal treatment
Compositions
Heat treating
29571, 29576B, 29578, 148187, 357 23, 357 45, 357 91, H01L 21265, B01J 1700
Patent
active
043560423
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention pertains to semiconductor memory circuits and in particular to the fabrication of bit patterns into the memory cells of a read only memory (ROM).
BACKGROUND ART
Read only memory circuits are manufactured to have a predetermined bit pattern permanently fixed in the memory cells. Fabrication of a ROM memory circuit starts with a blank silicon substrate and processing of the substrate requires a substantial number of manufacturing steps. A typical manufacturing cycle requires approximately 20 days. It has heretofore been the conventional practice to incorporate the customer bit pattern into the memory circuit at an early stage in the processing, for example, at contact etch. As circuit details have become smaller and designs incorporate shared column and data lines, ion implantation has been selected over the contact etch step to implant the desired threshold levels into the channel regions of the memory cells. This placed the programming step even earlier in the process sequence. In process time this meant that approximately 15 days elapsed between the time the programming step was implemented and the time the part was completed. The fixing of the bit pattern into the circuit at an early stage in the processing has a number of drawbacks. The primary problem is that of customer response time, that is, the time between receipt of the desired bit pattern by the manufacturer and the completion of the fabrication of the memory circuit. When the bit pattern is incorporated at a relatively early point in the manufacturing sequence, then the response time must include most of the steps in the entire manufacturing cycle.
A further problem is that the yield of good dies from a wafer cannot be determined until the memory cells are completely fabricated. Conventionally the memory cells cannot be parametrically or functionally tested until long after the bit pattern is encoded and the die is committed to a specific customer. Therefore, the manufacturer must commit a sufficient number of wafers to produce the number of parts ordered after estimating the losses which will be incurred in the manufacturing process. If the yield of products is lower than anticipated, there will be an insufficient number of parts to meet the customer's requirements and if the yield proves to be greater than expected there will be good parts produced for which there is no customer order.
Further, if there should be an error in the customer supplied programming pattern or if there should be a major flaw in the manufacturing process, the mistake will not be detected until the entire cycle is essentially complete. Once the error is found and corrected, the new parts will not be available until another complete manufacturing cycle is started and completed.
From the above it can be seen that the impact of these problems could be reduced if it were possible to delay the incorporation of the customer bit pattern into the read only memory circuit until a late stage in the manufacturing operation. This would make it possible for the manufacturer to build an inventory of uncommitted parts, to parametrically test these parts, and to provide a rapid customer response by completing only the final processing operations required to incorporate the customer bit pattern into the memory circuit.
Therefore, there exists a need for a manufacturing process for producing a reliable ROM circuit, but which delays the incorporation of the customer bit pattern until a late stage of processing.
SUMMARY OF THE INVENTION
The present invention relates to a method for producing a ROM semiconductor device having a selected bit pattern implanted therein. An illustrative embodiment method of the present invention comprises essentially the steps of:
(a) Fabricating a plurality of memory cells on a semiconductor substrate where the memory cells are separated by field oxide, each cell having doped source and drain regions in the substrate on each side of a non-implanted channel region, a gate oxide immediately above the channel region,
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Knepper, IBM-TDB, 15 (1973) 2919.
Gedaly Jerrell M.
Kirkland David D.
Sadowski Joseph P.
Sigmund Frank J.
Mostek Corporation
Roy Upendra
LandOfFree
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