Method for fabricating a semiconductor memory cell

Details Method for fabricating a semiconductor memory cell Method for fabricating a semiconductor memory cell

1992-03-12

1993-06-15

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 60, 437233, 437235, 437919, H01L 2170

Patent

active

052197808

ABSTRACT:
The present invention relates to a method for fabricating a semiconductor memory cell consisting of a switching transistor and a capacitor wherein a polysilicon pad and a polysilicon storage node are simultaneously patterned with a self-alignment method without a mask.
Accordingly, the present invention has the following advantages: First, the overlay accuracy can be improved by patterning a polysilicon pad and a polysilicon storage node with a self-alignment method. Second, the fabrication process can be simpler than the prior fabrication process for the semiconductor memory cell of a noble stacked capacitor cell structure. Third, the storage capacitance of a capacitor can be increased.

REFERENCES:
patent: 4742018 (1988-05-01), Kimura et al.

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