Method for fabricating a semiconductor memory

Details Method for fabricating a semiconductor memory Method for fabricating a semiconductor memory

1993-12-28

1996-04-16

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 60, 437229, 437919, H01L 218242

Patent

active

055082181

ABSTRACT:
A method for fabricating a semiconductor memory, including the steps of: forming a memory cell transistor having a gate electrode, a source area and a drain area on a semiconductor substrate; forming an insulating film over the memory cell transistor; forming an etch preventing film over the insulating film; forming multi-layer films over the etch preventing film by stacking alternately a disposable film and a conduction layer; selectively etching the multi-layer films corresponding to a contact hole to form a stacked film pattern; forming conductive sidewalls on sides of the stacked film pattern; forming a photoresist pattern on the stacked film pattern; selectively etching the etch preventing film and the insulating film by using the photoresist pattern and the conductive sidewall, and thereby forming the contact hole; forming an upper conductive film on the stacked film pattern and the contact hole including the conductive sidewall; patterning the upper conductive film and the stacked film pattern to thereby form a capacitor storage node pattern; and removing the disposable film.

REFERENCES:
patent: 4536949 (1985-08-01), Takayama et al.
patent: 5063176 (1991-11-01), Lee et al.
patent: 5155675 (1992-10-01), Oehrlein et al.
patent: 5268322 (1993-12-01), Lee et al.
patent: 5294561 (1994-03-01), Tanigawa
patent: 5389560 (1995-02-01), Ponki

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