Method for fabricating a semiconductor epitaxial wafer...

Single-crystal – oriented-crystal – and epitaxy growth processes; – Processes of growth from liquid or supercritical state – Having pulling during growth

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Reexamination Certificate

active

06776841

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor epitaxial wafer and method for making the same. More particularly, the present invention relates to a method for fabricating a semiconductor epitaxial wafer in which a silicon substrate is doped with carbon by melting chunks of polysilicon and carbon together, thereby effectively controlling interstitial silicon and thereby affecting a device-active region and thus realizing a very large scale integrated semiconductor device.
2. Description of the Prior Art
In general, wafer fabrication processes necessarily require ion implantation steps. The implantation of ions into silicon crystals, however, produces a great quantity of interstitial silicons. Such interstitial silicons cause a transient enhanced diffusion of boron during subsequent heat treatment steps, and also form a deep trap level within a silicon band gap. Furthermore, transient enhanced diffusion of boron often results in a reverse short channel effect in a short channel transistor, while the deep trap level gives rise to degradation in device characteristics, such as junction leakage current.
As a solution to these problems, prior art technology has used a proximate gettering methods in which carbon is implanted into a channel region to absorb the interstitial silicons. Although proximate gettering methods can advantageously suppress the transient enhanced diffusion of boron by implanted carbon, unfortunately, the carbon atoms may form another trap level causing an increase in junction leakage current.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method for fabricating semiconductor epitaxial wafers that are capable of suppressing an increase in junction leakage current due to a trap level formed by doped carbon.
Another object of the present invention is to provide a method for fabricating a semiconductor epitaxial wafers that are capable of improving an intrinsic gettering effect by forming many more intrinsic gettering regions.
These and other objects are attained in accordance with the present invention by a method for fabricating a semiconductor epitaxial wafer having doped carbon, the method comprising the steps of providing silicon containing carbon, growing an ingot from the silicon containing carbon, forming a silicon wafer with carbon by slicing the ingot and then surface-treating the sliced ingot, and growing an epitaxial silicon layer on a surface of the silicon wafer with carbon.
According to another aspect of the present invention, a method for fabricating a semiconductor epitaxial wafer having doped carbon, the method comprising the steps of mixing a quantity of carbon with a quantity of silicon and then melting together the quantities of carbon and silicon, growing an ingot from the melted silicon containing carbon, grinding the ingot so as to produce a flat surface and a notch, slicing the ingot into a piece of a silicon wafer having carbon, polishing the silicon wafer having carbon, and growing an epitaxial silicon layer on a surface of the polished silicon wafer having carbon, is provided.
According to another aspect of the present invention, a semiconductor epitaxial wafer, comprises a quantity of carbon contained within a quantity of silicon; an ingot formed from the silicon containing carbon; a silicon wafer having carbon obtained by slicing the ingot to obtain a plurality of rough wafers; and an epitaxial silicon layer formed on a surface of each silicon wafer having carbon.


REFERENCES:
patent: 5077143 (1991-12-01), Barraclough et al.
patent: 5360986 (1994-11-01), Candelaria
patent: 5441901 (1995-08-01), Candelaria
patent: 5498578 (1996-03-01), Steele et al.
patent: 5561302 (1996-10-01), Candelaria
patent: 5565690 (1996-10-01), Theodore et al.
patent: 5961944 (1999-10-01), Aratani et al.
patent: 6013564 (2000-01-01), Muramatsu
patent: 6059879 (2000-05-01), Gonzalez
patent: 6162708 (2000-12-01), Tamatsuka et al.
patent: 6204152 (2001-03-01), Falster et al.
patent: 6426265 (2002-07-01), Chu et al.
patent: 6491752 (2002-12-01), Kirscht et al.
patent: 2002/0100917 (2002-08-01), Chu et al.
patent: 2002/0121676 (2002-09-01), Chu et al.
patent: 2002/0179003 (2002-12-01), Iida et al.
patent: 1114044 (1989-05-01), None
patent: 5152179 (1993-06-01), None
patent: 7329054 (1995-12-01), None
patent: 9036080 (1997-02-01), None
patent: 9110595 (1997-04-01), None
patent: 10050639 (1998-02-01), None
patent: 10050715 (1998-02-01), None
patent: 11092300 (1999-04-01), None
patent: 11302098 (1999-11-01), None
patent: 11312683 (1999-11-01), None
patent: 077372 (2000-03-01), None
patent: 077380 (2000-03-01), None
patent: 272998 (2000-10-01), None
patent: 319099 (2000-11-01), None
patent: 2001237247 (2001-08-01), None
Wolf et al., Silicon Processing for the VLSI Era, vol. 1: Process Technology, Lattice Press, Sunset Beach, CA, USA, pp. 1-35, 59-61, 124-159, 1986.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for fabricating a semiconductor epitaxial wafer... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for fabricating a semiconductor epitaxial wafer..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating a semiconductor epitaxial wafer... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3317282

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.