Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2001-06-13
2003-08-12
Chaudhuri, Olik (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S750000, C257S751000, C257S383000
Reexamination Certificate
active
06605872
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and method for fabricating the same, and more particularly, to a semiconductor device and method for fabricating the same which is adapted to prevent the latch-up of the semiconductor device.
2. Discussion of Related Art
CMOS circuits generally experience feedback which leads to a latch-up of the device and a temporary or permanent loss of the circuit functions. The latch-up resulting from such feedback and disadvantages following therefrom will be briefly described below.
FIG. 1
is a cross-sectional view of a general CMOS transistor, and
FIG. 2
is an equivalent circuit diagram of the CMOS transistor shown in FIG.
1
.
As illustrated in
FIGS. 1 and 2
, the CMOS transistor has a p-type well
11
c
formed in a defined region of an n-type substrate
11
a
. P
+
-type impurity regions
11
b
, which are used as the emitter of a pnp-type transistor, are formed in the surface of the substrate
11
a
. Similarly, n
+
-type impurity regions
11
d
used as the emitter of an npn-type transistor are formed in the surface of the substrate
11
a
corresponding to the p-type well
11
c.
Consequently, the p
+
-type impurity regions
11
b
, n-type substrate
11
a
and p-type well
11
c
form a pnp-type positive transistor in the horizontal direction, while the n
+
-type impurity regions
11
d
, p-type well
11
c
and n-type substrate
11
a
form a npn-type positive transistor vertically. The bases of those two transistors provide positive feedback paths which are respectively driven by the collectors of different transistors.
Actually, a parasitic pnpn-junction is formed by the p- and n-junctions in providing both of the pnp- and npn-type transistors. Such a pnpn-junction is an unexpected result in the CMOS transistor and causes a deterioration in the characteristics of the device. That is, the pnpn-junction gives rise to a latch-up affecting the operation of the CMOS transistor.
As shown in
FIGS. 1 and 2
, a resistance R
W
is induced by series resistances in the p-type well
11
c
with respect to the current flowing into the p
+
-type impurity regions
11
b
. Reference symbol R
S
indicates the resistance value of the substrate with respect to the n
+
-type impurity regions
11
d
. The current flowing across the resistance R
S
can be calculated from the resistance value R
S
. The resistance value R
S
of the substrate may be obtained, but that of the p-type well
11
c
is hard to calculate due to non-uniform dopants and thickness of the depletion layer.
As described previously, the parasitic pnpn-junction has an influence upon the operation of the CMOS transistor and may be prevented by increasing the space between the devices. However, with increases in device integration, the space between the devices is reduced and the pnpn-junction is inevitable.
A method for fabricating a semiconductor device in accordance with prior art will be described in connection with
FIGS. 3
a
-
3
e
, which are cross-sectional views of the conventional semiconductor device at different stages during the fabrication process conventionally employed.
As shown in
FIG. 3
a
, a silicon oxide layer
32
is formed via an oxidation of the surface of an n-type semiconductor substrate
31
.
As shown in
FIG. 3
b
, the silicon oxide layer
32
is eliminated in the region in which an n-channel transistor will be formed. A p-type impurity is then doped and diffused so as to form a p-type well region
33
.
As shown in
FIGS. 3
c
, the silicon oxide layer
32
is selectively eliminated in the region in which the source and drain of a p-channel transistor will be formed on the surface of the n-type substrate
31
. A p-type impurity is highly doped to form p
+
-type impurity regions
34
.
As shown in
FIG. 3
d
, the silicon oxide layer
32
is selectively eliminated in order to form the source and drain of the n-channel transistor in the p-type well region
33
. An n-type impurity is then doped and diffused, forming n
+
-type impurity regions
35
.
As shown in
FIG. 3
e
, there are formed gate electrodes
36
and
36
a
of the n- and p-channel transistors, respectively, so that the semiconductor device of the prior art is completed.
Such a conventional fabrication of a semiconductor device however involves a disadvantage in that the resistance of the well R
w
cannot be reduced below a particular sheet resistance specified by the characteristics of the device in applying a substrate bias through the contact or the like after the completion of the fabrication.
SUMMARY OF THE INVENTION
The present invention is directed to a semiconductor device and method for fabricating the same that substantially obviates one or more of the above or other problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a semiconductor device and method for fabricating the same which is adapted to prevent a latch-up, thereby enhancing the reliability of the device by forming a buried layer comprising conductive layer patterns on the surface of a wafer.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a semiconductor device includes: conductive layer patterns formed on a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate and the conductive layer patterns; well regions formed in the semiconductor layer and the semiconductor substrate such that the conductive layer patterns are positioned at the bottoms of the well regions; and gate and source/drain electrodes formed on the well regions.
In another aspect of the present invention, a method for fabricating a semiconductor device includes the steps of: forming conductive layer patterns on a semiconductor substrate, forming a semiconductor layer on the semiconductor substrate including the conductive layer patterns; forming well regions in the semiconductor layer and the semiconductor substrate such that the conductive layer patterns are positioned at the bottoms of the well regions; and forming gate and source/drain electrodes on the well regions.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4216489 (1980-08-01), Clemens et al.
patent: 4229756 (1980-10-01), Sato et al.
patent: 4654121 (1987-03-01), Miller et al.
patent: 4710897 (1987-12-01), Masuoka et al.
patent: 4745453 (1988-05-01), Mizutani
patent: 4808545 (1989-02-01), Balasubramanyam et al.
patent: 4859630 (1989-08-01), Josquin
patent: 4866291 (1989-09-01), Shimada et al.
patent: 5229307 (1993-07-01), Vora et al.
patent: 5420061 (1995-05-01), Manning
patent: 5478761 (1995-12-01), Komori et al.
patent: 5519240 (1996-05-01), Suzuki
patent: 5668755 (1997-09-01), Hidaka
patent: 5679981 (1997-10-01), Kuwajima
patent: 5696016 (1997-12-01), Chen et al.
patent: 5702968 (1997-12-01), Chen
patent: 5705426 (1998-01-01), Hibino
patent: 5831313 (1998-11-01), Han et al.
patent: 5855826 (1999-01-01), Lee et al.
patent: 5915179 (1999-06-01), Etou et al.
patent: 6043552 (2000-03-01), Miwa
patent: 6274416 (2001-08-01), Kim et al.
patent: 6388278 (2002-05-01), Suzuki et al.
patent: 59222957 (1984-12-01), None
Kim Dong Hoon
Lee Joong Jin
Birch & Stewart Kolasch & Birch, LLP
Chaudhuri Olik
LG Electronics Inc.
Schillinger Laura
LandOfFree
Method for fabricating a semiconductor device including a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating a semiconductor device including a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating a semiconductor device including a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3113538