Method for fabricating a semiconductor device having a shallow t

Details Method for fabricating a semiconductor device having a shallow t Method for fabricating a semiconductor device having a shallow t

1997-06-20

1999-05-18

Dang, Trung

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438434, 438435, 438524, 438525, 148DIG50, H01L21/76

Patent

active

059045418

ABSTRACT:
A semiconductor device having a shallow trench isolation structure, where the upper part of the trench is broader than the lower part of it, comprises an insulating layer on the sidewalls of the upper part of the trench, another insulating layer buried in the trench for isolating semiconductor devices and low-concentration doped regions near the upper part of the trench and high-concentration doped regions near the lower part of the trench. Therefore, the leakage current is prevented due to the sufficient amount of the ions in the high-concentration doped regions near the lower part of the trench and the narrow width effect is minimized owing to the insulating layer on the sidewalls of the upper part of the trench.

REFERENCES:
patent: 4472240 (1984-09-01), Kameyama
patent: 4580330 (1986-04-01), Pollack et al.
patent: 5401998 (1995-03-01), Chiu et al.
patent: 5436190 (1995-07-01), Yang et al.

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