Method for fabricating a semiconductor device having a multi-lay

Details Method for fabricating a semiconductor device having a multi-lay Method for fabricating a semiconductor device having a multi-lay

1992-11-24

1994-08-02

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437238, 437228, 148DIG118, H01L 2190

Patent

active

053345525

ABSTRACT:
A method of fabricating a multi-layered interconnection structure which comprises the steps of: forming a first wiring layer on a silicon oxide film having a compressive stress; forming a thick (2 to 3.5 .mu.m) fluorine-containing silicon oxide film at a temperature not higher than 200 .degree. C.; etching back the fluorine-containing silicon oxide film to flatten the surface of the film; forming a silicon oxide film having a compressive stress; forming a through-hole in position; and forming a second wiring layer. Since the fluorine-containing silicon oxide film is used as part of an insulating film, a resistance to cracking, flatness and reliability are significantly improved.

REFERENCES:
patent: 4894352 (1990-01-01), Lane et al.
patent: 5215787 (1993-06-01), Homma

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