Method for fabricating a semiconductor device by slope etching a

Details Method for fabricating a semiconductor device by slope etching a Method for fabricating a semiconductor device by slope etching a

1990-05-02

1992-02-18

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 46, 437 47, 437 48, 437 52, 437228, 437233, 437919, H01L 2170

Patent

active

050894366

ABSTRACT:
This invention provides a method for manufacturing a semiconductor device which prevents residues from remaining around an etching pattern of a poly-silicon by making the poly-silicon be gradiently etched out. An oxide barrier layer is deposited over a poly-silicon layer, and impurities are implanted through the oxide barrier layer, wherein the concentration difference of impurities makes the poly-silicon have a graded sidewalls, and the value of resistance is controlled by the quantity of impurities. After removing the oxide barrier layer the poly-silicon is selectively etched into a poly electrode having a graded sidewall. The thermal treatment of the poly electrode is carried out and a polysilicon for another electrode is deposited and etched out.

REFERENCES:
patent: 3756861 (1973-09-01), Payne et al.
patent: 3936331 (1976-02-01), Lue et al.
patent: 3980507 (1976-09-01), Carley
patent: 4057895 (1977-11-01), Ghezzo
patent: 4240196 (1980-12-01), Jacobs et al.
patent: 4349408 (1982-09-01), Tarng et al.
patent: 4350536 (1982-09-01), Nakano et al.
patent: 4364779 (1982-12-01), Kamgar
patent: 4370798 (1983-02-01), Lien et al.
patent: 4503601 (1985-03-01), Chiao
patent: 4609429 (1986-09-01), Ishaq et al.
patent: 4702000 (1987-10-01), Matlock et al.
Coburn, "Plasma Assisted Etching", Plasma Chemistry and Plasma Processing, vol. 2, No. 1, 1982, pp. 1-41.
Rideout, "Double Polysilicon Dynamic Random-Access Memory Cell with Increased Change Storage Capacitance", IBM TDB, vol. 21, No. 9, Feb. 1979.
Yhomdhi, "VLSI Fabrication Principles", John Wiley & Sons, 1983, pp. 353-34.

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