Method for fabricating a semiconductor device

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including adhesive bonding step

Reexamination Certificate

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C257S758000, C257S759000

Reexamination Certificate

active

06908793

ABSTRACT:
A process for fabricating a semiconductor device having, for example, a MISFET transistor, is provided which comprises the steps of (a) providing a partially fabricated semiconductor device comprising a substrate and a first and second polysilican layer insulatively spaced from the substrate by an insulating layer, the insulating layer having an opening therein which exposes the surface of the first polysilicon layer positioned below the second polysilicon layer and (b) exposing the partially fabricated semiconductor device to a noble gas halide to substantially remove the first polysilicon layer.

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Patent Abstracts of Japan JP 11 004023 A (NEC Corp), Jun. 1, 1999 abstract.
Anonymous: “Directional Etching With XeF(2) and Other Active Gases, Sep. 1979.” OIBM Technical Disclosure Bulletin, vol. 22, No. 4, Sep. 1, 1979, p. 1640.
Dissertation: “The Application of Photoluminescence to the Optimization of Indium Phosphate MIS Technology (Indium Phosphate, Phosphate)”,Ray R. Chang, vol. 50-12B, PP 5790 (194 pages); Colorado State University, 1989.
Correlation of Tensile Properties to the Amounts of Gas Porosity in Permanent Mold Test Bars, M. J. Young, Conference: Transactions of the American Foundrymen's Society v 89., AFS, DesPlaines, Illinois pp. 465-468, 1982.
Surface-micromachined accelerometer using a movalbe polysilicon gate FET, Jae-Hoon Chung and James Jungho Pak; Proc. SPIE—Int. Soc. Opt. Eng. (USA), vol. 3242, pp 96-104, 1997.
Study on InP MIS FET using photo-assisted CVD, T. Sugano, F. Arai, and H. Okasaki; Annu. Rep. Eng. Res. Inst. Fac. Eng. Univ. Tokyo (Japan), vol. 49, pp. 87-92, Sep. 1990.

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