Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Having diverse electrical device
Reexamination Certificate
2002-01-31
2004-05-18
Kang, Donghee (Department: 2811)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Having diverse electrical device
C438S022000, C438S042000, C438S046000, C438S047000, C438S707000, C438S708000, C438S718000, C438S796000
Reexamination Certificate
active
06737288
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for fabricating a semiconductor device and, more particularly, to an etching method used in the method for fabricating a semiconductor device.
2. Description of the Related Art
To constitute various types of semiconductor devices including, for example, laser diodes, GaAs-FET and HEMT, a hetero junction structure has been used to improve the characteristics of the semiconductor device. In order to arrange a good-quality hetero junction structure, the lattice constants of both materials should be substantially coincident with each other.
In the field of semiconductor lasers, for example, there has been proposed the reduction of a threshold current by use of a so-called heterojunction structure wherein an emission region having a small band gap energy be sandwiched between semiconductor layers having a large band gap energy. Since then, it has been known to prepare a heterojunction structure of good quality using GaAs and Al
x
Ga
1−x
As, thereby forming a GaAs-AlGaAs double heterojunction laser.
The Al
x
Ga
1−x
As material exhibits an increasing band gap energy Eg with an; increase in x, and, although the refractive index n decreases, the change in lattice constant is very small.
In the selective etching at the interface of growth of a hetero junction structure for the formation of a semiconductor device having the hetero junction structure, the etching is stopped only due to the difference in chemical etching rate between a layer to be etched and a layer for stopping the etching. Accordingly, it is necessary that the ratio in etching rate between the layer to be etched and the layer for stopping the etching be 50 or more.
This makes it difficult to stop the etching with high accuracy depending on the types of materials for the layer to be etched and the layer for stopping the etching in the course of selective etching, even though an Al
x
Ga
1−x
As material capable of forming a high-quality heterojunction is used. This entails much time for the choice of an etching solution and also an appreciable limitation placed on the choice of materials used to constitute a semiconductor device.
FIG. 13
is a perspective view showing a conventional semiconductor laser. In
FIG. 13
, indicated by
100
is a semiconductor laser, by
101
is an n-type GaAs substrate (n-type is hereinafter referred to as “n-”, and likewise, p-type is referred to as “p-”), by
102
is a buffer layer made of n-GaAs, by
103
is an n-type clad layer made of n-Al
0.5
Ga
0.5
As, by
104
is a multiple quantum well active layer made of Al
0.35
Ga
0.65
As/Al
0.15
Ga
0.85
As, by
105
is a first p-type clad layer made of p-Al
0.5
Ga
0.5
As, by
106
is an etching stopper layer made of p-Al
0.2
Ga
0.8
As, by
107
is a current block layer made of Al
0.6
Ga
0.4
As, by
108
is an opening of the current block layer
107
, by
109
is a surface protective layer made of n-GaAs, by
110
is a second p-type clad layer made of p-Al
0.5
Ga
0.5
As, by
111
is a contact layer made of p-GaAs, by
112
is a removed region of the contact layer
111
, by
113
is a p electrode, and by
114
is an n electrode.
Next, a method of fabricating a conventional semiconductor laser is described.
FIGS. 14 and 15
are, respectively, a sectional view showing a semiconductor laser at one stage in a conventional method of fabricating a semiconductor laser.
FIGS. 14 and 15
are, respectively, a sectional view taken along line XIV—XIV of FIG.
13
.
Referring to
FIG. 14
, after successive deposition, on the n-GaAs substrate via the buffer layer
102
, of the n-type clad layer
103
, the multiple quantum well active layer
104
, the first p-type clad layer
105
, the etching stopper layer
106
, the current block layer
107
and the surface protective layer
109
, a resist film is formed on the surface of the surface protective layer
109
to form a resist pattern having a band-shaped opening along a direction of an optical waveguide. The surface protective layer
109
is subjected to patterning by use of a photolithographic technique using the resist pattern as a mask. Subsequently, after removal of the mask pattern of the resist film, the current block layer
107
is selectively etched through the mask of the patterned surface protective layer
109
until the etching stopper layer
106
is exposed, thereby forming a band-shaped opening
108
in the current block layer
107
.
Thereafter, the second p-type clad layer
110
and the contact layer
111
are successively built up on the current block layer
107
including the opening
108
and the surface protective layer
109
.
A resist film is formed on the surface of the contact layer
111
, and a resist pattern
115
having an opening is formed in the vicinity of opposite end faces of the band-shaped opening
108
, followed by selective etching of the contact layer
111
through the resist pattern
115
used as a mask to form the removed region
112
of the contact layer
111
. The results provided by the selective etching step are shown in FIG.
14
.
For selective etching and removing the contact layer
111
, a mixture of ammonia and hydrogen peroxide is used as an etching solution.
With reference to
FIG. 15
, the resist patter
115
is removed and the p electrode
113
is formed, and the n-GaAs substrate
101
is polished at a back side thereof to a given thickness, followed by formation of the n electrode
114
. The results of these steps are shown in FIG.
15
.
The etching solution (a mixed solution of ammonia and an aqueous hydrogen peroxide solution) used in the selective etching for removal of the contact layer
111
carried out in the conventional fabrication method serves to stop the etching by using only the difference in chemical etching rate between GaAs used for the contact layer
111
and Al
0.5
Ga
0.5
As used for the second p-type clad layer
110
. Accordingly, it is necessary that the ratio of the etching rate between the GaAs of the layer to be etched and the Al
x
Ga
1−x
As of the etching stop layer be 50 or over. To this end, it is necessary that the compositional ratio of Al in the etching stop layer be at 0.2 or over.
In this case, the etching stop layer is constituted of the second p-type clad layer
110
, so that the compositional ratio of Al can be set at 0.5, thereby ensuring a satisfactory etching rate ratio to GaAs. In general, however, such conditions are not always ensured, and thus, the selective etching of a compound semiconductor subjected to hetero junction has suffered a substantial limitation depending on the type of heterojunctioned material, which has, in turn, placed considerable limitations on the selection and structure of constituting materials of a semiconductor device.
Though a satisfactory etching rate ratio has been ensured, the control of carrying out etching to a necessary and sufficient extent is quite difficult, under which overetching leads to side etching. If a mixed solution of ammonia and an aqueous hydrogen peroxide solution is provided as an etching solution, surface oxidation takes place violently, thus being undesirable from the standpoint of surface morphology.
It will be noted that known techniques are described in Japanese Patent Laid-Open Nos. Hei 01-099276, Sho 61-077384 and Sho 62-176183, which disclose techniques of improving the accuracy of selective etching.
In Japanese Patent Laid-Open No. Hei 01-099276, there is disclosed a method using tartaric acid as an etching solution.
Moreover, in Appl. Phys. Lett. 55(10), Sep. 4, 1989, p. 984-p. 986, photochemical etching is described wherein a laser beam from a GaAs/AlGaAs hetero structure is irradiated.
SUMMARY OF THE INVENTION
The present invention has been made to overcome the above-described drawbacks and disadvantages of the related art. It is an object of the present invention to provide a method for fabricating a semiconductor device comprising the step of accurately stopping selective etching at the interface of a hetero junction arrangement.
According to one aspect of
Kawazu Zempei
Yagi Tetsuya
LandOfFree
Method for fabricating a semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating a semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating a semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3251153