Method for fabricating a self-spaced contact for semiconductor d

Details Method for fabricating a self-spaced contact for semiconductor d Method for fabricating a self-spaced contact for semiconductor d

1994-10-17

1995-12-19

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 41, 437913, 437 56, H01L 21823

Patent

active

054768039

ABSTRACT:
A method for fabricating semiconductor devices with a self-spaced contact is provided. Spacing required between the self-spaced contact and a gate region is lessened, thus reducing chip size, and parasitic capacitance and resistance. A transistor region includes a gate and diffusion region. A pad oxide layer comprises an uppermost layer of the gate. A spacer oxide is formed on side walls of the gate region. The thickness of the pad oxide layer controls the width of the spacer oxide region. The spacer oxide insulates the gate from the diffusion regions, so that electrical contacts may be formed close to the gate for reducing the overall size of the semiconductor device. The doping structure of the diffusion regions is controlled by the width of the spacer oxide regions. Thus, the doping structure of the diffusions can be altered to reduce parasitic capacitance and resistance.

REFERENCES:
patent: 4745080 (1988-05-01), Scovell et al.
patent: 4883767 (1989-11-01), Gray et al.
patent: 4886764 (1989-12-01), Miller et al.
patent: 4966858 (1990-10-01), Masquelier et al.
patent: 4992387 (1991-02-01), Tamura
patent: 5028555 (1991-09-01), Haskell
patent: 5049525 (1991-09-01), Coleman, Jr.
patent: 5098854 (1992-03-01), Kapoor et al.
patent: 5100838 (1992-03-01), Dennison
patent: 5106783 (1992-04-01), Chin et al.
patent: 5149664 (1992-09-01), Shin et al.
patent: 5175127 (1992-12-01), Manning
patent: 5183773 (1993-02-01), Miyata
patent: 5217913 (1993-06-01), Watabe et al.
patent: 5217923 (1993-06-01), Suguro
patent: 5227319 (1993-07-01), Ogura et al.
patent: 5393685 (1995-02-01), Yoo et al.

Affiliated with

Also associated with

Rating

Method for fabricating a self-spaced contact for semiconductor d does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for fabricating a self-spaced contact for semiconductor d, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating a self-spaced contact for semiconductor d will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-991869