Method for fabricating a self-aligned T-gate metal semiconductor

Details Method for fabricating a self-aligned T-gate metal semiconductor Method for fabricating a self-aligned T-gate metal semiconductor

1994-12-19

1996-03-05

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 41, 437 42, 437 44, 437944, H01L 21265

Patent

active

054967791

ABSTRACT:
Disclosed is a method of fabricating a metal semiconductor field effect transistor, comprising the steps for, forming the channel using an ion-implantation, sequentially forming a first insulator layer at a first predetermined temperature and a second insulation layer at second predetermined temperature over the surface of the substrate, etching the first and second insulation layers using a gate pattern of a photo-resist pattern to expose the channel region as a mask, forming a refractory metal over the surface of the first and second insulation layer add the exposed channel region, etching the refractory metal, thereby dividing it into two parts of which one is formed on the channel region and the other is formed on the second insulation layer, selectively etching the first and second insulation layers to lift-off the refractory metal over the first and second insulation layers, thereby forming a gate of a T-shape on the channel region, ion implanting Si into a substrate using the gate and a channel pattern of a photo-resist film to form a self-aligned high concentration ion implantation region, forming a third insulation layer for preventing As of evaporation, carrying out a rapid thermal annealing for activation, removing the third insulation layer; and forming an ohmic electrode using a lift-off process.

REFERENCES:
patent: 4959326 (1990-09-01), Roman et al.
patent: 5053348 (1991-10-01), Mishra et al.
patent: 5182218 (1993-01-01), Fujihira
patent: 5288654 (1994-02-01), Kasai et al.
patent: 5300445 (1994-04-01), Oku
patent: 5334542 (1994-08-01), Saito et al.
patent: 5369044 (1994-11-01), Shimura

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